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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-24 15:20:23 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-24 15:20:23 +0200 |
| commit | 8043c90a04031c1619d0be7b1aba717e4f9968ac (patch) | |
| tree | 2c6f5fb2768459a6d9f32295563225157cf5d049 /picorv32.v | |
| parent | bec8d6a6b966ce494d50a37a257af9f8cc3c8b01 (diff) | |
| download | picorv32-8043c90a04031c1619d0be7b1aba717e4f9968ac.tar.gz picorv32-8043c90a04031c1619d0be7b1aba717e4f9968ac.zip | |
Added REGS_INIT_ZERO parameter
Diffstat (limited to 'picorv32.v')
| -rw-r--r-- | picorv32.v | 11 |
1 files changed, 11 insertions, 0 deletions
@@ -58,6 +58,7 @@ module picorv32 #( parameter [ 0:0] ENABLE_IRQ = 0, parameter [ 0:0] ENABLE_IRQ_QREGS = 1, parameter [ 0:0] ENABLE_IRQ_TIMER = 1, + parameter [ 0:0] REGS_INIT_ZERO = 0, parameter [31:0] MASKED_IRQ = 32'h 0000_0000, parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, @@ -135,6 +136,14 @@ module picorv32 #( reg [31:0] irq_pending; reg [31:0] timer; + integer i; + initial begin + if (REGS_INIT_ZERO) begin + for (i = 0; i < regfile_size; i = i+1) + cpuregs[i] = 0; + end + end + `ifdef DEBUGREGS wire [31:0] dbg_reg_x0 = cpuregs[0]; wire [31:0] dbg_reg_x1 = cpuregs[1]; @@ -1882,6 +1891,7 @@ module picorv32_axi #( parameter [ 0:0] ENABLE_IRQ = 0, parameter [ 0:0] ENABLE_IRQ_QREGS = 1, parameter [ 0:0] ENABLE_IRQ_TIMER = 1, + parameter [ 0:0] REGS_INIT_ZERO = 0, parameter [31:0] MASKED_IRQ = 32'h 0000_0000, parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, @@ -1983,6 +1993,7 @@ module picorv32_axi #( .ENABLE_IRQ (ENABLE_IRQ ), .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ), .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ), + .REGS_INIT_ZERO (REGS_INIT_ZERO ), .MASKED_IRQ (MASKED_IRQ ), .LATCHED_IRQ (LATCHED_IRQ ), .PROGADDR_RESET (PROGADDR_RESET ), |