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author | Clifford Wolf <clifford@clifford.at> | 2016-08-31 00:08:33 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-08-31 00:08:33 +0200 |
commit | 82d837bf9610675de84ff4cf1f6998573a63257d (patch) | |
tree | ba6403e8a97f2fe14794e6fed85d82aa862f51be /picorv32.v | |
parent | 12c218c1b3c4d13b404b1630b9977bade4a0ac52 (diff) | |
download | picorv32-82d837bf9610675de84ff4cf1f6998573a63257d.tar.gz picorv32-82d837bf9610675de84ff4cf1f6998573a63257d.zip |
Be more explicit about single register file write port
Diffstat (limited to 'picorv32.v')
-rw-r--r-- | picorv32.v | 20 |
1 files changed, 16 insertions, 4 deletions
@@ -1063,6 +1063,9 @@ module picorv32 #( if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem"; end + reg cpuregs_write; + reg [31:0] cpuregs_wrdata; + reg set_mem_do_rinst; reg set_mem_do_rdata; reg set_mem_do_wdata; @@ -1169,6 +1172,8 @@ module picorv32 #( trap <= 0; reg_sh <= 'bx; reg_out <= 'bx; + cpuregs_write = 0; + cpuregs_wrdata = 'bx; set_mem_do_rinst = 0; set_mem_do_rdata = 0; set_mem_do_wdata = 0; @@ -1264,25 +1269,32 @@ module picorv32 #( latched_branch: begin current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) : reg_next_pc; `debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);) - cpuregs[latched_rd] <= reg_pc + (latched_compr ? 2 : 4); + cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4); + cpuregs_write = 1; end latched_store && !latched_branch: begin `debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);) - cpuregs[latched_rd] <= latched_stalu ? alu_out_q : reg_out; + cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out; + cpuregs_write = 1; end ENABLE_IRQ && irq_state[0]: begin - cpuregs[latched_rd] <= current_pc | latched_compr; + cpuregs_wrdata = current_pc | latched_compr; + cpuregs_write = 1; current_pc = PROGADDR_IRQ; irq_active <= 1; mem_do_rinst <= 1; end ENABLE_IRQ && irq_state[1]: begin eoi <= irq_pending & ~irq_mask; - cpuregs[latched_rd] <= irq_pending & ~irq_mask; + cpuregs_wrdata = irq_pending & ~irq_mask; + cpuregs_write = 1; next_irq_pending = next_irq_pending & irq_mask; end endcase + if (cpuregs_write) + cpuregs[latched_rd] <= cpuregs_wrdata; + if (ENABLE_TRACE && latched_trace) begin latched_trace <= 0; trace_valid <= 1; |