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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-08 22:31:03 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-08 22:31:03 +0200 |
| commit | 51be28263354fdfc1029e31c4c8fc49c5cfe61ba (patch) | |
| tree | 81a6443455eb282e72774c8aa91dfee5827e4636 /scripts | |
| parent | dd30b57ea6d799b0e2112f1fb130f1bc6df5f86e (diff) | |
| download | picorv32-51be28263354fdfc1029e31c4c8fc49c5cfe61ba.tar.gz picorv32-51be28263354fdfc1029e31c4c8fc49c5cfe61ba.zip | |
Updated evaluation
Diffstat (limited to 'scripts')
| -rw-r--r-- | scripts/vivado/synth_area_large.tcl | 3 | ||||
| -rw-r--r-- | scripts/vivado/synth_area_regular.tcl | 3 | ||||
| -rw-r--r-- | scripts/vivado/synth_area_small.tcl | 3 | ||||
| -rw-r--r-- | scripts/vivado/tabtest.sh | 3 | ||||
| -rw-r--r-- | scripts/vivado/tabtest.v | 2 |
5 files changed, 9 insertions, 5 deletions
diff --git a/scripts/vivado/synth_area_large.tcl b/scripts/vivado/synth_area_large.tcl index 55b0248..af611b5 100644 --- a/scripts/vivado/synth_area_large.tcl +++ b/scripts/vivado/synth_area_large.tcl @@ -3,7 +3,8 @@ read_verilog synth_area_top.v read_xdc synth_area.xdc synth_design -part xc7k70t-fbg676 -top top_large -opt_design -resynth_seq_area +opt_design -sweep -propconst -resynth_seq_area +opt_design -directive ExploreSequentialArea report_utilization report_timing diff --git a/scripts/vivado/synth_area_regular.tcl b/scripts/vivado/synth_area_regular.tcl index d7a8e34..2bf6b4c 100644 --- a/scripts/vivado/synth_area_regular.tcl +++ b/scripts/vivado/synth_area_regular.tcl @@ -3,7 +3,8 @@ read_verilog synth_area_top.v read_xdc synth_area.xdc synth_design -part xc7k70t-fbg676 -top top_regular -opt_design -resynth_seq_area +opt_design -sweep -propconst -resynth_seq_area +opt_design -directive ExploreSequentialArea report_utilization report_timing diff --git a/scripts/vivado/synth_area_small.tcl b/scripts/vivado/synth_area_small.tcl index c9a8a22..11d2104 100644 --- a/scripts/vivado/synth_area_small.tcl +++ b/scripts/vivado/synth_area_small.tcl @@ -3,7 +3,8 @@ read_verilog synth_area_top.v read_xdc synth_area.xdc synth_design -part xc7k70t-fbg676 -top top_small -opt_design -resynth_seq_area +opt_design -sweep -propconst -resynth_seq_area +opt_design -directive ExploreSequentialArea report_utilization report_timing diff --git a/scripts/vivado/tabtest.sh b/scripts/vivado/tabtest.sh index b481014..4ebd925 100644 --- a/scripts/vivado/tabtest.sh +++ b/scripts/vivado/tabtest.sh @@ -28,7 +28,8 @@ synth_case() { read_verilog ../../../picorv32.v read_xdc test_${1}.xdc synth_design -flatten_hierarchy full -part ${xl_device} -top top - opt_design -sweep -remap + opt_design -sweep -remap -propconst + opt_design -directive Explore place_design -directive Explore phys_opt_design -retime -rewire -critical_pin_opt -placement_opt -critical_cell_opt route_design -directive Explore diff --git a/scripts/vivado/tabtest.v b/scripts/vivado/tabtest.v index de75b11..cdf2057 100644 --- a/scripts/vivado/tabtest.v +++ b/scripts/vivado/tabtest.v @@ -73,7 +73,7 @@ module top ( delay4 #(32) delay_eoi (clk, eoi , io_eoi ); picorv32_axi #( - .TWO_CYCLE_COMPARE(1) + .TWO_CYCLE_ALU(1) ) cpu ( .clk (clk ), .resetn (resetn ), |