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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-25 14:08:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-25 14:08:39 +0200 |
| commit | 23b700cf73b7b01b4737db106226bd4220799290 (patch) | |
| tree | 27a6109332ccf71c4a3b284d05a74d1ab3ac14ed /testbench.v | |
| parent | 982e5cc60085236be18a5be35f3747e480ed549f (diff) | |
| download | picorv32-23b700cf73b7b01b4737db106226bd4220799290.tar.gz picorv32-23b700cf73b7b01b4737db106226bd4220799290.zip | |
Added basic IRQ support
Diffstat (limited to 'testbench.v')
| -rw-r--r-- | testbench.v | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/testbench.v b/testbench.v index c14122d..b9914f5 100644 --- a/testbench.v +++ b/testbench.v @@ -6,6 +6,7 @@ module testbench; reg clk = 1; reg resetn = 0; + wire irq = &uut.picorv32_core.count_cycle[12:0]; wire trap; always #5 clk = ~clk; @@ -37,9 +38,14 @@ module testbench; wire mem_axi_rready; reg [31:0] mem_axi_rdata; - picorv32_axi uut ( + picorv32_axi #( + .ENABLE_EXTERNAL_IRQ (1), + .ENABLE_ILLINSTR_IRQ (1), + .ENABLE_TIMER_IRQ (1) + ) uut ( .clk (clk ), .resetn (resetn ), + .irq (irq ), .trap (trap ), .mem_axi_awvalid(mem_axi_awvalid), .mem_axi_awready(mem_axi_awready), |