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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-17 15:23:58 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-17 15:23:58 +0100 |
| commit | c7cc32ed95644b50a1cd22e2005cacdba5b63388 (patch) | |
| tree | 007de2bb814819f44b17ac8797eb3b9238949eda /testbench.v | |
| parent | e4312b0fab053cda38cb46623341db85e9f8a060 (diff) | |
| download | picorv32-c7cc32ed95644b50a1cd22e2005cacdba5b63388.tar.gz picorv32-c7cc32ed95644b50a1cd22e2005cacdba5b63388.zip | |
Fix verilog code for modelsim
Diffstat (limited to 'testbench.v')
| -rw-r--r-- | testbench.v | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/testbench.v b/testbench.v index 84a2fd0..e113265 100644 --- a/testbench.v +++ b/testbench.v @@ -12,7 +12,6 @@ module testbench #( parameter AXI_TEST = 0, parameter VERBOSE = 0 ); - reg clk = 1; reg resetn = 0; wire trap; @@ -75,8 +74,6 @@ module picorv32_wrapper #( output trace_valid, output [35:0] trace_data ); - - wire trap; wire tests_passed; reg [31:0] irq; @@ -234,7 +231,6 @@ module axi4_memory #( output reg tests_passed ); - reg [31:0] memory [0:64*1024/4-1] /* verilator public */; reg verbose; initial verbose = $test$plusargs("verbose") || VERBOSE; |