Fix indenting in wishbone code

1 files changed, 78 insertions, 86 deletions

diff --git a/testbench_wb.v b/testbench_wb.v
index eee3040..a613e50 100644
--- a/testbench_wb.v
+++ b/testbench_wb.v
@@ -75,26 +75,25 @@ module picorv32_wrapper #(
 		irq[5] = &uut.picorv32_core.count_cycle[15:0];
 	end
 
-wire [31:0] wb_m2s_adr;
-wire [31:0] wb_m2s_dat;
-wire [3:0] wb_m2s_sel;
-wire wb_m2s_we;
-wire wb_m2s_cyc;
-wire wb_m2s_stb;
-//wire [2:0] wb_m2s_cti;
-reg [2:0] wb_m2s_cti = 3'b000;
-wire [1:0] wb_m2s_bte;
-wire [31:0] wb_s2m_dat;
-wire wb_s2m_ack;
-wire wb_s2m_err;
-wire wb_s2m_rty;
+	wire [31:0] wb_m2s_adr;
+	wire [31:0] wb_m2s_dat;
+	wire [3:0] wb_m2s_sel;
+	wire wb_m2s_we;
+	wire wb_m2s_cyc;
+	wire wb_m2s_stb;
+	//wire [2:0] wb_m2s_cti;
+	reg [2:0] wb_m2s_cti = 3'b000;
+	wire [1:0] wb_m2s_bte;
+	wire [31:0] wb_s2m_dat;
+	wire wb_s2m_ack;
+	wire wb_s2m_err;
+	wire wb_s2m_rty;
 
 	wb_ram #(
 		.depth (16384 * 4),
 		.memfile ("firmware/firmware.hex"),
 		.VERBOSE (VERBOSE)
-	)
-	ram (// Wishbone interface
+	) ram ( // Wishbone interface
 		.wb_clk_i(wb_clk),
 		.wb_rst_i(wb_rst),
 
@@ -111,7 +110,7 @@ wire wb_s2m_rty;
 		.wb_err_o(),
 
 		.tests_passed(tests_passed)
-		);
+	);
 
 	picorv32_wb #(
 `ifndef SYNTH_TEST
@@ -166,34 +165,33 @@ wire wb_s2m_rty;
 	end
 endmodule
 
-module wb_ram
-	#(//Wishbone parameters
-		parameter dw = 32,
-		//Memory parameters
-		parameter depth = 256,
-		parameter aw = 32,
-		parameter memfile = "",
-		parameter VERBOSE = 0
-	)
-	(
-		input wb_clk_i,
-		input wb_rst_i,
-
-		input [aw-1:0] wb_adr_i,
-		input [dw-1:0] wb_dat_i,
-		input [3:0] wb_sel_i,
-		input wb_we_i,
-		input [1:0] wb_bte_i,
-		input [2:0] wb_cti_i,
-		input wb_cyc_i,
-		input wb_stb_i,
-
-		output reg wb_ack_o,
-		output wb_err_o,
-		output reg [dw-1:0] wb_dat_o,
-
-		output reg tests_passed
-	);
+module wb_ram #(
+	//Wishbone parameters
+	parameter dw = 32,
+	//Memory parameters
+	parameter depth = 256,
+	parameter aw = 32,
+	parameter memfile = "",
+	parameter VERBOSE = 0
+) (
+	input wb_clk_i,
+	input wb_rst_i,
+
+	input [aw-1:0] wb_adr_i,
+	input [dw-1:0] wb_dat_i,
+	input [3:0] wb_sel_i,
+	input wb_we_i,
+	input [1:0] wb_bte_i,
+	input [2:0] wb_cti_i,
+	input wb_cyc_i,
+	input wb_stb_i,
+
+	output reg wb_ack_o,
+	output wb_err_o,
+	output reg [dw-1:0] wb_dat_o,
+
+	output reg tests_passed
+);
 
 	localparam CLASSIC_CYCLE = 1'b0;
 	localparam BURST_CYCLE   = 1'b1;
@@ -214,40 +212,40 @@ module wb_ram
 		BTE_WRAP_16 = 2'd3;
 
 	function wb_is_last;
-	input [2:0] cti;
-	begin
-		case (cti)
-		CTI_CLASSIC      : wb_is_last = 1'b1;
-		CTI_CONST_BURST  : wb_is_last = 1'b0;
-		CTI_INC_BURST    : wb_is_last = 1'b0;
-		CTI_END_OF_BURST : wb_is_last = 1'b1;
-		default : $display("%d : Illegal Wishbone B3 cycle type (%b)", $time, cti);
-		endcase
-	end
+		input [2:0] cti;
+		begin
+			case (cti)
+				CTI_CLASSIC      : wb_is_last = 1'b1;
+				CTI_CONST_BURST  : wb_is_last = 1'b0;
+				CTI_INC_BURST    : wb_is_last = 1'b0;
+				CTI_END_OF_BURST : wb_is_last = 1'b1;
+				default : $display("%d : Illegal Wishbone B3 cycle type (%b)", $time, cti);
+			endcase
+		end
 	endfunction
 
 	function [31:0] wb_next_adr;
-	input [31:0] adr_i;
-	input [2:0] cti_i;
-	input [2:0] bte_i;
-	input integer dw;
-
-	reg [31:0] adr;
-	integer shift;
-	begin
-		shift = $clog2(dw/8);
-		adr = adr_i >> shift;
-		if (cti_i == CTI_INC_BURST)
-			case (bte_i)
-			BTE_LINEAR   : adr = adr + 1;
-			BTE_WRAP_4   : adr = {adr[31:2], adr[1:0]+2'd1};
-			BTE_WRAP_8   : adr = {adr[31:3], adr[2:0]+3'd1};
-			BTE_WRAP_16  : adr = {adr[31:4], adr[3:0]+4'd1};
-			endcase // case (burst_type_i)
-
-		wb_next_adr = adr << shift;
-	end
-endfunction
+		input [31:0] adr_i;
+		input [2:0] cti_i;
+		input [2:0] bte_i;
+		input integer dw;
+
+		reg [31:0] adr;
+		integer shift;
+		begin
+			shift = $clog2(dw/8);
+			adr = adr_i >> shift;
+			if (cti_i == CTI_INC_BURST)
+				case (bte_i)
+				BTE_LINEAR   : adr = adr + 1;
+				BTE_WRAP_4   : adr = {adr[31:2], adr[1:0]+2'd1};
+				BTE_WRAP_8   : adr = {adr[31:3], adr[2:0]+3'd1};
+				BTE_WRAP_16  : adr = {adr[31:4], adr[3:0]+4'd1};
+				endcase // case (burst_type_i)
+
+			wb_next_adr = adr << shift;
+		end
+	endfunction
 
 	reg verbose;
 	initial verbose = $test$plusargs("verbose") || VERBOSE;
@@ -269,8 +267,7 @@ endfunction
 
 	wire [aw-1:0] adr = new_cycle ? wb_adr_i : next_adr;
 
-	always @(posedge wb_clk_i)
-	begin
+	always @(posedge wb_clk_i) begin
 		adr_r <= adr;
 		valid_r <= valid;
 		// Ack generation
@@ -308,9 +305,7 @@ endfunction
 	end
 
 	always @(posedge wb_clk_i) begin
-
-		if (waddr2 < 64 * 1024 / 4)
-		begin
+		if (waddr2 < 64 * 1024 / 4) begin
 			if (we[0])
 				mem[waddr2][7:0] <= wb_dat_i[7:0];
 
@@ -336,11 +331,8 @@ endfunction
 		wb_dat_o <= mem[raddr2];
 	end
 
-	generate
-		initial
-		if (memfile != "") begin
+	initial begin
+		if (memfile != "")
 			$readmemh(memfile, mem);
-		end
-	endgenerate
-
+	end
 endmodule