picorv32 - Fork of https://github.com/YosysHQ/picorv32.

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix initialization of "irq" in verilog testbench	Clifford Wolf	2019-09-22	1	-1/+1
*	Improve test firmware, increase testbench memory size to 128kB	Clifford Wolf	2019-09-12	1	-4/+2
*	Do not peek into core for cycle count in WB testbench	Clifford Wolf	2019-06-03	1	-2/+5
*	testbench_wb: Add proper attribution for wb_ram module	Olof Kindgren	2017-12-27	1	-0/+19
*	testbench_wb: Load firmware with plusarg instead of parameter	Olof Kindgren	2017-12-27	1	-1/+7
*	Add testbench_ez	Clifford Wolf	2017-07-27	1	-1/+1
*	testbench_wb.v: unify verbose output with axi testbench	Antony Pavlov	2017-04-06	1	-7/+22
*	testbench_wb.v: drop unused stuff	Antony Pavlov	2017-03-17	1	-96/+11
*	testbench_wb.v: fix output stuff	Antony Pavlov	2017-03-15	1	-8/+7
*	Fix indenting in wishbone code	Clifford Wolf	2017-03-14	1	-86/+78
*	WIP: add WISHBONE testbench	Antony Pavlov	2017-03-14	1	-0/+346