testbench_wb.v: unify verbose output with axi testbench

Unification of testbench output makes it possible to use the diff
utility for comparing testbench instruction traces.

Alas the testbench and testbench_wb traces are differ
because of interrupts, e.g.

    picorv32$ make testbench_wb.vvp
    iverilog -o testbench_wb.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench_wb.v picorv32.v
    chmod -x testbench_wb.vvp
    picorv32$ make testbench.vvp
    iverilog -o testbench.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench.v picorv32.v
    chmod -x testbench.vvp
    picorv32$ vvp -N testbench_wb.vvp +verbose | head -n 856 > /tmp/testbench_wb.log
    picorv32$ vvp -N testbench.vvp +verbose | head -n 856 > /tmp/testbench.log
    picorv32$ diff -u /tmp/testbench.log /tmp/testbench_wb.log
    --- /tmp/testbench.log  2017-04-06 06:56:06.079804549 +0300
    +++ /tmp/testbench_wb.log       2017-04-06 06:55:58.763485130 +0300
    @@ -850,7 +850,7 @@
     RD: ADDR=000056a0 DATA=00000013 INSN
     RD: ADDR=000056a4 DATA=fff00113 INSN
     RD: ADDR=000056a8 DATA=00000013 INSN
    -RD: ADDR=000056ac DATA=14208463 INSN  <--- testbench: no interrupt
    -RD: ADDR=000056b0 DATA=00120213 INSN
    -RD: ADDR=000056b4 DATA=00200293 INSN
    -RD: ADDR=000056b8 DATA=fe5212e3 INSN
    +RD: ADDR=00000010 DATA=0200a10b INSN  <--- testbench_wb: interrupt
    +RD: ADDR=00000014 DATA=0201218b INSN
    +RD: ADDR=00000018 DATA=000000b7 INSN
    +RD: ADDR=0000001c DATA=16008093 INSN

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>

1 files changed, 22 insertions, 7 deletions

diff --git a/testbench_wb.v b/testbench_wb.v
index 808b770..5bccc0b 100644
--- a/testbench_wb.v
+++ b/testbench_wb.v
@@ -68,6 +68,7 @@ module picorv32_wrapper #(
 );
 	wire tests_passed;
 	reg [31:0] irq;
+	wire mem_instr;
 
 	always @* begin
 		irq = 0;
@@ -101,6 +102,7 @@ module picorv32_wrapper #(
 		.wb_sel_i(wb_m2s_sel),
 		.wb_we_i(wb_m2s_we),
 
+		.mem_instr(mem_instr),
 		.tests_passed(tests_passed)
 	);
 
@@ -122,6 +124,7 @@ module picorv32_wrapper #(
 		.irq (irq),
 		.trace_valid (trace_valid),
 		.trace_data (trace_data),
+		.mem_instr(mem_instr),
 
 		.wb_clk_i(wb_clk),
 		.wb_rst_i(wb_rst),
@@ -175,6 +178,7 @@ module wb_ram #(
 	output reg wb_ack_o,
 	output reg [31:0] wb_dat_o,
 
+	input mem_instr,
 	output reg tests_passed
 );
 
@@ -209,13 +213,28 @@ module wb_ram #(
 	reg [31:0] mem [0:depth/4-1] /* verilator public */;
 
 	always @(posedge wb_clk_i) begin
-		if (ram_we)
+		if (ram_we) begin
+			if (verbose)
+				$display("WR: ADDR=%08x DATA=%08x STRB=%04b",
+					adr_r, wb_dat_i, we);
+
 			if (adr_r[31:0] == 32'h1000_0000)
-				$write("%c", wb_dat_i[7:0]);
+				if (verbose) begin
+					if (32 <= wb_dat_i[7:0] && wb_dat_i[7:0] < 128)
+						$display("OUT: '%c'", wb_dat_i[7:0]);
+					else
+						$display("OUT: %3d", wb_dat_i[7:0]);
+				end else begin
+					$write("%c", wb_dat_i[7:0]);
+`ifndef VERILATOR
+					$fflush();
+`endif
+				end
 			else
 			if (adr_r[31:0] == 32'h2000_0000)
 				if (wb_dat_i[31:0] == 123456789)
 					tests_passed = 1;
+		end
 	end
 
 	always @(posedge wb_clk_i) begin
@@ -232,15 +251,11 @@ module wb_ram #(
 			if (we[3])
 				mem[waddr2][31:24] <= wb_dat_i[31:24];
 
-			if (ram_we)
-				if (verbose)
-					$display("WR: ADDR=%08x DATA=%08x STRB=%04b",
-						adr_r, wb_dat_i, we);
 		end
 
 		if (valid & wb_ack_o & !ram_we)
 			if (verbose)
-				$display("RD: ADDR=%08x DATA=%08x%s", adr_r, mem[raddr2], 0 ? " INSN" : "");
+				$display("RD: ADDR=%08x DATA=%08x%s", adr_r, mem[raddr2], mem_instr ? " INSN" : "");
 
 		wb_dat_o <= mem[raddr2];
 	end