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* Fix initialization of "irq" in verilog testbenchClifford Wolf2019-09-221-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve test firmware, increase testbench memory size to 128kBClifford Wolf2019-09-121-4/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Do not peek into core for cycle count in WB testbenchClifford Wolf2019-06-031-2/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* testbench_wb: Add proper attribution for wb_ram moduleOlof Kindgren2017-12-271-0/+19
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* testbench_wb: Load firmware with plusarg instead of parameterOlof Kindgren2017-12-271-1/+7
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* Add testbench_ezClifford Wolf2017-07-271-1/+1
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* testbench_wb.v: unify verbose output with axi testbenchAntony Pavlov2017-04-061-7/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unification of testbench output makes it possible to use the diff utility for comparing testbench instruction traces. Alas the testbench and testbench_wb traces are differ because of interrupts, e.g. picorv32$ make testbench_wb.vvp iverilog -o testbench_wb.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench_wb.v picorv32.v chmod -x testbench_wb.vvp picorv32$ make testbench.vvp iverilog -o testbench.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench.v picorv32.v chmod -x testbench.vvp picorv32$ vvp -N testbench_wb.vvp +verbose | head -n 856 > /tmp/testbench_wb.log picorv32$ vvp -N testbench.vvp +verbose | head -n 856 > /tmp/testbench.log picorv32$ diff -u /tmp/testbench.log /tmp/testbench_wb.log --- /tmp/testbench.log 2017-04-06 06:56:06.079804549 +0300 +++ /tmp/testbench_wb.log 2017-04-06 06:55:58.763485130 +0300 @@ -850,7 +850,7 @@ RD: ADDR=000056a0 DATA=00000013 INSN RD: ADDR=000056a4 DATA=fff00113 INSN RD: ADDR=000056a8 DATA=00000013 INSN -RD: ADDR=000056ac DATA=14208463 INSN <--- testbench: no interrupt -RD: ADDR=000056b0 DATA=00120213 INSN -RD: ADDR=000056b4 DATA=00200293 INSN -RD: ADDR=000056b8 DATA=fe5212e3 INSN +RD: ADDR=00000010 DATA=0200a10b INSN <--- testbench_wb: interrupt +RD: ADDR=00000014 DATA=0201218b INSN +RD: ADDR=00000018 DATA=000000b7 INSN +RD: ADDR=0000001c DATA=16008093 INSN Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
* testbench_wb.v: drop unused stuffAntony Pavlov2017-03-171-96/+11
| | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
* testbench_wb.v: fix output stuffAntony Pavlov2017-03-151-8/+7
| | | | | | | | | | | | | | | This patch fixes wishbone testbench output issue: 'DNNE' instead of 'DONE', i.e. Cycle counter ......... 546536 Instruction counter .... 69770 CPI: 7.83 DNNE ------------------------------------------------------------ EBREAK instruction at 0x000006C4 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
* Fix indenting in wishbone codeClifford Wolf2017-03-141-86/+78
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* WIP: add WISHBONE testbenchAntony Pavlov2017-03-141-0/+346
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
generated by cgit (git 2.34.1) at 2024-05-19 19:17:00 +0000