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* README.md: Document the meaning of mem_instrJonathan Neuschäfer2016-04-031-1/+2
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* Improvements in icestorm test firmwareClifford Wolf2015-07-311-7/+35
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* icestorm sim improvementsClifford Wolf2015-07-213-6/+38
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* Improved icestorm exampleClifford Wolf2015-07-193-13/+11
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* Improved icestorm exampleClifford Wolf2015-07-199-76/+226
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* Added $(VIVADO_BASE) to vivado MakefileClifford Wolf2015-07-161-4/+5
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* Improved firmware for vivado "system" exampleClifford Wolf2015-07-165-9/+41
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* Improved vivado "system" exampleClifford Wolf2015-07-122-16/+56
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* Vivado "system" exampleClifford Wolf2015-07-0910-21/+142
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* Updated evaluationClifford Wolf2015-07-091-9/+9
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* Refactoring of TWO_CYCLE_ALUClifford Wolf2015-07-081-143/+117
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* Updated evaluationClifford Wolf2015-07-086-18/+22
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* Added TWO_CYCLE_ALU parameterClifford Wolf2015-07-082-52/+136
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* Enabled report_timing in vivado synth_area scriptsClifford Wolf2015-07-084-4/+4
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* Updated eval dataClifford Wolf2015-07-083-12/+26
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* Added TWO_CYCLE_COMPAREClifford Wolf2015-07-072-8/+29
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* Updated RV32I tools instructionsClifford Wolf2015-07-051-4/+4
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* Improved IceStorm example scriptClifford Wolf2015-07-043-1/+75
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* Added -WerrorClifford Wolf2015-07-041-1/+1
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* c++/c99-style for loops in firmwareClifford Wolf2015-07-044-11/+7
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* Turned gcc warnings up to elevenClifford Wolf2015-07-046-17/+19
| | | | Patch by Larry Doolittle
* Fixed typo in MakefileClifford Wolf2015-07-031-1/+1
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* Added missing LD_RS1 debug statementsClifford Wolf2015-07-021-3/+10
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* Updated area and timing statsClifford Wolf2015-07-022-10/+11
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* Being more aggressive with parallel casesClifford Wolf2015-07-021-145/+173
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* Added TWO_STAGE_SHIFT parameterClifford Wolf2015-07-022-1/+11
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* Added `debug macroClifford Wolf2015-07-021-42/+27
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* Minor Makefile changesClifford Wolf2015-07-022-4/+5
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* Removed trailing whitespaces in dhrystone codeClifford Wolf2015-07-024-61/+61
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* Removed trailing whitespacesClifford Wolf2015-07-0213-15/+15
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* Unsigned arguments for print_dec()Clifford Wolf2015-07-024-7/+7
| | | | Patch by Larry Doolittle
* Some testbench-related improvementsClifford Wolf2015-07-022-4/+13
| | | | Patch by Larry Doolittle
* Updated evaluationClifford Wolf2015-07-021-21/+34
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* Back to Vivado 2015.1Clifford Wolf2015-07-012-3/+3
| | | | my synthesis license has a 2015.05 version limit..
* Vivado 2015.2 area evaluationClifford Wolf2015-07-016-20/+15
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* Added vivado synth_area_{small,regular,large}.tcl scriptsClifford Wolf2015-07-014-4/+33
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* Updated Xilinx 7-Series area statsClifford Wolf2015-07-012-23/+19
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* Added CATCH_MISALIGN and CATCH_ILLINSNClifford Wolf2015-07-012-8/+23
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* After some profiling: one-hot FSM encodingClifford Wolf2015-07-011-9/+10
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* Spelling fixes by Larry DoolittleClifford Wolf2015-07-011-10/+10
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* Improvements in PCPI MUL coreClifford Wolf2015-06-301-10/+15
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* Added TOC to READMEClifford Wolf2015-06-302-1/+16
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* Added "make test_synth"Clifford Wolf2015-06-303-2/+22
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* Added Note about Icarus Verilog to READMEClifford Wolf2015-06-291-0/+5
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* Added LATCHED_IRQ parameterClifford Wolf2015-06-292-1/+14
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* Minor README changeClifford Wolf2015-06-291-1/+6
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* Added ENABLE_IRQ_QREGS and ENABLE_IRQ_TIMERClifford Wolf2015-06-283-13/+130
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* Improved start.S IRQ codeClifford Wolf2015-06-281-3/+8
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* Cleanups in PCPI interfaceClifford Wolf2015-06-282-73/+133
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* Fixed typo in firmware/start.SClifford Wolf2015-06-281-1/+1
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