Commit message (Expand) | Author | Age | Files | Lines | ||
---|---|---|---|---|---|---|
... | ||||||
* | Removed unnecessary "jal" complexity | Clifford Wolf | 2015-06-09 | 1 | -4/+1 | |
* | Small improvements in vivado_soc demo | Clifford Wolf | 2015-06-08 | 1 | -5/+4 | |
* | Added osu018 yosys synthesis script | Clifford Wolf | 2015-06-08 | 6 | -1/+10 | |
* | Refactored instruction decoder | Clifford Wolf | 2015-06-08 | 3 | -174/+223 | |
* | Improved timing for "decoded_imm_uj" | Clifford Wolf | 2015-06-07 | 1 | -4/+3 | |
* | README Updates | Clifford Wolf | 2015-06-07 | 1 | -2/+6 | |
* | Added support for dual-port register file | Clifford Wolf | 2015-06-07 | 2 | -21/+74 | |
* | minor optimizations | Clifford Wolf | 2015-06-07 | 1 | -5/+7 | |
* | Improved "decoder_trigger" handling | Clifford Wolf | 2015-06-07 | 1 | -14/+11 | |
* | Added look-ahead write interface | Clifford Wolf | 2015-06-07 | 3 | -58/+73 | |
* | Major redesign of main FSM | Clifford Wolf | 2015-06-07 | 8 | -303/+287 | |
* | Using libc assembler code in dhrystone stdlib.c | Clifford Wolf | 2015-06-07 | 5 | -4/+606 | |
* | Updated CPI table in README | Clifford Wolf | 2015-06-06 | 1 | -9/+11 | |
* | Updated README | Clifford Wolf | 2015-06-06 | 1 | -6/+16 | |
* | Added insn timing hack to dryhstone testbench | Clifford Wolf | 2015-06-06 | 1 | -1/+15 | |
* | Added memory "look-ahead" read interface | Clifford Wolf | 2015-06-06 | 3 | -28/+36 | |
* | Improved Xilinx example | Clifford Wolf | 2015-06-06 | 6 | -10/+69 | |
* | Faster memory model in dhrystone testbench | Clifford Wolf | 2015-06-06 | 1 | -18/+18 | |
* | Improved AXI tests | Clifford Wolf | 2015-06-06 | 2 | -73/+90 | |
* | Added license info to README | Clifford Wolf | 2015-06-06 | 1 | -0/+3 | |
* | Improved AXI Interface Testbench | Clifford Wolf | 2015-06-06 | 2 | -35/+110 | |
* | Initial import | Clifford Wolf | 2015-06-06 | 60 | -0/+6250 |