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* Improved firmware for vivado "system" exampleClifford Wolf2015-07-165-9/+41
* Improved vivado "system" exampleClifford Wolf2015-07-122-16/+56
* Vivado "system" exampleClifford Wolf2015-07-0910-21/+142
* Updated evaluationClifford Wolf2015-07-091-9/+9
* Refactoring of TWO_CYCLE_ALUClifford Wolf2015-07-081-143/+117
* Updated evaluationClifford Wolf2015-07-086-18/+22
* Added TWO_CYCLE_ALU parameterClifford Wolf2015-07-082-52/+136
* Enabled report_timing in vivado synth_area scriptsClifford Wolf2015-07-084-4/+4
* Updated eval dataClifford Wolf2015-07-083-12/+26
* Added TWO_CYCLE_COMPAREClifford Wolf2015-07-072-8/+29
* Updated RV32I tools instructionsClifford Wolf2015-07-051-4/+4
* Improved IceStorm example scriptClifford Wolf2015-07-043-1/+75
* Added -WerrorClifford Wolf2015-07-041-1/+1
* c++/c99-style for loops in firmwareClifford Wolf2015-07-044-11/+7
* Turned gcc warnings up to elevenClifford Wolf2015-07-046-17/+19
* Fixed typo in MakefileClifford Wolf2015-07-031-1/+1
* Added missing LD_RS1 debug statementsClifford Wolf2015-07-021-3/+10
* Updated area and timing statsClifford Wolf2015-07-022-10/+11
* Being more aggressive with parallel casesClifford Wolf2015-07-021-145/+173
* Added TWO_STAGE_SHIFT parameterClifford Wolf2015-07-022-1/+11
* Added `debug macroClifford Wolf2015-07-021-42/+27
* Minor Makefile changesClifford Wolf2015-07-022-4/+5
* Removed trailing whitespaces in dhrystone codeClifford Wolf2015-07-024-61/+61
* Removed trailing whitespacesClifford Wolf2015-07-0213-15/+15
* Unsigned arguments for print_dec()Clifford Wolf2015-07-024-7/+7
* Some testbench-related improvementsClifford Wolf2015-07-022-4/+13
* Updated evaluationClifford Wolf2015-07-021-21/+34
* Back to Vivado 2015.1Clifford Wolf2015-07-012-3/+3
* Vivado 2015.2 area evaluationClifford Wolf2015-07-016-20/+15
* Added vivado synth_area_{small,regular,large}.tcl scriptsClifford Wolf2015-07-014-4/+33
* Updated Xilinx 7-Series area statsClifford Wolf2015-07-012-23/+19
* Added CATCH_MISALIGN and CATCH_ILLINSNClifford Wolf2015-07-012-8/+23
* After some profiling: one-hot FSM encodingClifford Wolf2015-07-011-9/+10
* Spelling fixes by Larry DoolittleClifford Wolf2015-07-011-10/+10
* Improvements in PCPI MUL coreClifford Wolf2015-06-301-10/+15
* Added TOC to READMEClifford Wolf2015-06-302-1/+16
* Added "make test_synth"Clifford Wolf2015-06-303-2/+22
* Added Note about Icarus Verilog to READMEClifford Wolf2015-06-291-0/+5
* Added LATCHED_IRQ parameterClifford Wolf2015-06-292-1/+14
* Minor README changeClifford Wolf2015-06-291-1/+6
* Added ENABLE_IRQ_QREGS and ENABLE_IRQ_TIMERClifford Wolf2015-06-283-13/+130
* Improved start.S IRQ codeClifford Wolf2015-06-281-3/+8
* Cleanups in PCPI interfaceClifford Wolf2015-06-282-73/+133
* Fixed typo in firmware/start.SClifford Wolf2015-06-281-1/+1
* Fixed PCPI instr prefetchingClifford Wolf2015-06-282-5/+5
* Added resource utilization to xilinx evalClifford Wolf2015-06-285-20/+173
* Improvements in picorv32_pcpi_mulClifford Wolf2015-06-284-21/+53
* More README stuffClifford Wolf2015-06-284-0/+55
* Moved ENABLE_MUL from picorv32_axi to picorv32Clifford Wolf2015-06-282-59/+85
* Improved IRQ documentation, added assembler macrosClifford Wolf2015-06-2812-77/+182