| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | RISC-V ISA 2.1 now calls "sbreak" officially "ebreak" | Clifford Wolf | 2016-06-06 | 1 | -1/+1 |
| * | Added ENABLE_DIV and picorv32_pcpi_div | Clifford Wolf | 2016-04-10 | 4 | -0/+164 |
| * | Bump riscv-gnu-toolchain version | Clifford Wolf | 2015-12-16 | 2 | -127/+4 |
| * | Removed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
| * | Added mul tests from riscv-tests | Clifford Wolf | 2015-06-27 | 5 | -0/+331 |
| * | Major redesign of main FSM | Clifford Wolf | 2015-06-07 | 1 | -53/+0 |
| * | Initial import | Clifford Wolf | 2015-06-06 | 41 | -0/+3588 |
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index : picorv32 | |
| Fork of https://github.com/YosysHQ/picorv32. |
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