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diff --git a/presentation/ExampleRun/output2/fuzz_1/reduce_sim_yosys.v b/presentation/ExampleRun/output2/fuzz_1/reduce_sim_yosys.v
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+++ b/presentation/ExampleRun/output2/fuzz_1/reduce_sim_yosys.v
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+// -*- mode: verilog -*-
+module top  (y, clk, wire0, wire1, wire2, wire3);
+  output wire  [(32'hb7):(32'h0)] y  ;
+  input wire  [(1'h0):(1'h0)] clk  ;
+  input wire signed [(5'h11):(1'h0)] wire0  ;
+  input wire signed [(4'ha):(1'h0)] wire1  ;
+  input wire  [(4'hd):(1'h0)] wire2  ;
+  input wire  [(4'h8):(1'h0)] wire3  ;
+   reg  [(2'h3):(1'h0)] reg5 = (1'h0) ;
+   reg  [(5'h14):(1'h0)] reg6 = (1'h0) ;
+   reg signed [(5'h12):(1'h0)] reg7 = (1'h0) ;
+   reg  [(4'hd):(1'h0)] reg8 = (1'h0) ;
+  assign y = {reg5, reg6, reg7, reg8} ;
+  always
+    @(posedge clk) begin
+      reg5 <=  (1'h0);
+      reg6 <=  wire1;
+      reg7 <=  ((~|((wire0 & {wire3,
+          (1'h0)}) | $unsigned(((1'h0) != (8'h9d))))) <<< ((wire1[(2'h2):(2'h2)] + ((~(8'ha7)) ?
+              wire3 : $signed(wire1))) ?
+          $unsigned(((^wire0) + $unsigned(wire3))) : (((reg5 * wire3) ?
+                  wire1 : $unsigned(reg6)) ?
+              {{(1'h0), wire2}} : (reg5[(1'h0):(1'h0)] ?
+                  $signed((1'h0)) : (~wire3)))));
+      reg8 <=  (~^$unsigned(reg6));
+    end
+endmodule
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