| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | actual_correct.v | 288 | logstatsplain |
| -rw-r--r-- | actual_wrong.v | 288 | logstatsplain |
| d--------- | equiv_identity_yosys | 33 | logstatsplain |
| d--------- | identity | 489 | logstatsplain |
| -rw-r--r-- | reduce_identity_yosys.v | 267 | logstatsplain |
| -rw-r--r-- | reduce_sim_yosys.v | 1059 | logstatsplain |
| d--------- | yosys | 39 | logstatsplain |
 |
index : fpga20_fubfst | |
| Finding and understanding bugs in FPGA synthesis tools. |
| summaryrefslogtreecommitdiffstats |