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author | John Wickerson <j.wickerson@imperial.ac.uk> | 2021-04-16 09:26:31 +0000 |
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committer | overleaf <overleaf@localhost> | 2021-04-16 09:26:36 +0000 |
commit | 004bd0b86c72ccf7a1e24526c7b5184cd8486b7e (patch) | |
tree | b819bb6eb78d7276bea6a615c8ba05e4d31b3e63 | |
parent | 5d6d12fc45930ac97ee85fc1286adaa52aa0577e (diff) | |
download | oopsla21_fvhls-004bd0b86c72ccf7a1e24526c7b5184cd8486b7e.tar.gz oopsla21_fvhls-004bd0b86c72ccf7a1e24526c7b5184cd8486b7e.zip |
Update on Overleaf.
-rw-r--r-- | algorithm.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/algorithm.tex b/algorithm.tex index 855208d..c214392 100644 --- a/algorithm.tex +++ b/algorithm.tex @@ -150,7 +150,7 @@ module main(reset, clk, finish, return_val); endcase endmodule \end{minted} -\caption{Verilog produced by \vericert{}. It demonstrates the instantiation of the RAM (lines 9--15), \JW{Sorry about the absolu} the data-path (lines 16--32) and the control logic (lines 33--42).}\label{fig:accumulator_v} +\caption{Verilog produced by \vericert{}. It demonstrates the instantiation of the RAM (lines 9--15), \JW{Sorry about the magic numbers here} the data-path (lines 16--32) and the control logic (lines 33--42).}\label{fig:accumulator_v} \end{subfigure} \caption{Translating a simple program from C to Verilog.}\label{fig:accumulator_c_rtl} \end{figure} |