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authorJohn Wickerson <>2020-11-12 12:34:32 +0000
committerJohn Wickerson <>2020-11-12 12:34:32 +0000
commitfae93d199b799b3b7ecf9900cec81e548de99d83 (patch)
tree7491c04f93022a4b931f4ef976d68a50be09c086
parent6f0cf440a54d6a112e94e3cd32e538df222ed61b (diff)
parentc6fcc3d366c9a39fce73c1e5d20b7c0bdf515c86 (diff)
downloadoopsla21_fvhls-fae93d199b799b3b7ecf9900cec81e548de99d83.tar.gz
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Merge branch 'master' of https://git.overleaf.com/5ed78033b633200001e693d0
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The \compcert{} semantics for the \texttt{Oshrximm} instruction express it's operation exactly as shown in the equation above, even though in hardware the computation that would be performed would be different. In \vericert{}, if the same operation would be implemented using Verilog operators, it is not guaranteed to be optimised correctly by the synthesis tools that convert the Verilog into a circuit. To guarantee an output that does not include divides, we therefore have to express it in Verilog using shifts, and then prove that this representation is equivalent to the divide representation used in the \compcert{} semantics. This proof discovered quite a few bugs in our initial implementation of optimisations, which rounded to $-\infty$ instead of 0.
+\subsection{Coq Mechanisation}
+
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