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| author | Yann Herklotz <git@yannherklotz.com> | 2021-09-10 15:46:02 +0100 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2021-09-10 15:46:02 +0100 |
| commit | a61f0a5b3a4664f2e1f42e788cc195a7d56ade28 (patch) | |
| tree | db56fb1c2ee34e2834ea90bb5743f8bd5977a397 /algorithm.tex | |
| parent | c53674cda775192d380e1423706b66d4b7c6050c (diff) | |
| download | oopsla21_fvhls-a61f0a5b3a4664f2e1f42e788cc195a7d56ade28.tar.gz oopsla21_fvhls-a61f0a5b3a4664f2e1f42e788cc195a7d56ade28.zip | |
Make the diagram larger and add copyright
Diffstat (limited to 'algorithm.tex')
| -rw-r--r-- | algorithm.tex | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/algorithm.tex b/algorithm.tex index a4941d5..0182d70 100644 --- a/algorithm.tex +++ b/algorithm.tex @@ -35,7 +35,7 @@ The .NET framework has been used as a basis for other HLS tools, such as Kiwi~\c continuation/.style={}, linecount/.style={rounded corners=3pt,dashed}] \fill[compcert,rounded corners=3pt] (-1,-0.5) rectangle (9.9,2); - \fill[formalhls,rounded corners=3pt] (-1,-1) rectangle (9.9,-2); + \fill[formalhls,rounded corners=3pt] (-1,-1) rectangle (9.9,-2.4); %\draw[linecount] (-0.95,-0.45) rectangle (3.6,1); %\draw[linecount] (4,-0.45) rectangle (7.5,1); \node[language] at (-0.3,0) (clight) {Clight}; @@ -54,7 +54,7 @@ The .NET framework has been used as a basis for other HLS tools, such as Kiwi~\c %%\node[anchor=west] at (-0.9,0.7) {\small $\sim$ 27 kloc}; %%\node[anchor=west] at (4.1,0.7) {\small $\sim$ 46 kloc}; %%\node[anchor=west] at (2,-1.5) {\small $\sim$ 17 kloc}; - \node[align=center] at (3.5,-2.4) {\footnotesize RAM\\[-0.5em]\footnotesize insertion}; + \node[align=center] at (3.2,-2) {\footnotesize RAM\\[-0.5em]\footnotesize insertion}; \draw[->,thick] (clight) -- (conta); \draw[->,thick] (conta) -- (cminor); \draw[->,thick] (cminor) -- (rtl); @@ -67,7 +67,7 @@ The .NET framework has been used as a basis for other HLS tools, such as Kiwi~\c \draw[->,thick] (htl) -- (verilog); \draw[->,thick] (htl.west) to [out=180,in=150] (4,-2.2) to [out=330,in=270] (htl.south); \end{tikzpicture}%} - \caption{\vericert{} as a Verilog back end to \compcert{}. \JW{The placement of the `RAM insertion' label suggests that it's not part of Vericert. Maybe move it inside the orange rectangle?}}% + \caption{\vericert{} as a Verilog back end to \compcert{}.}% \label{fig:rtlbranch} \end{figure} |