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author | Yann Herklotz <git@yannherklotz.com> | 2021-04-14 00:37:38 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2021-04-14 00:37:38 +0100 |
commit | 7c65e3ed3d9c8ef722aae52816d85e3486ca8de2 (patch) | |
tree | 0ee53f538cdcf03a0cdf0dd22e4936c53f3d08f6 /data | |
parent | 2e70aee3a563ca6c78c75be1922c9f657a3fc40a (diff) | |
download | oopsla21_fvhls-7c65e3ed3d9c8ef722aae52816d85e3486ca8de2.tar.gz oopsla21_fvhls-7c65e3ed3d9c8ef722aae52816d85e3486ca8de2.zip |
Update main diagram
Diffstat (limited to 'data')
-rw-r--r-- | data/accumulator.c | 9 | ||||
-rw-r--r-- | data/accumulator.htl | 38 | ||||
-rw-r--r-- | data/accumulator.rtl | 20 | ||||
-rw-r--r-- | data/accumulator.v | 173 |
4 files changed, 51 insertions, 189 deletions
diff --git a/data/accumulator.c b/data/accumulator.c index aa7171a..f8b5e32 100644 --- a/data/accumulator.c +++ b/data/accumulator.c @@ -1,9 +1,4 @@ int main() { - int x[3] = {1, 2, 3}; - int sum = 0; - for (int i = 0; - i < 3; - i++) - sum += x[i]; - return sum; + int x[1] = {3}; + return x[0]; } diff --git a/data/accumulator.htl b/data/accumulator.htl index f7bdb8e..ecab36f 100644 --- a/data/accumulator.htl +++ b/data/accumulator.htl @@ -1,38 +1,16 @@ main() { datapath { - 15: reg_8 <= 32'd1; - 14: reg_12[32'd0] <= reg_8; - 13: reg_7 <= 32'd2; - 12: reg_12[32'd1] <= reg_7; - 11: reg_6 <= 32'd3; - 10: reg_12[32'd2] <= reg_6; - 9: reg_2 <= 32'd0; - 8: reg_1 <= 32'd0; - 7: reg_5 <= 32'd0; - 6: reg_4 <= reg_12[{{{reg_5 + 32'd0} + {reg_1 * 32'd4}} / 32'd4}]; - 5: reg_2 <= {{reg_2 + reg_4} + 32'd0}; - 4: reg_1 <= {reg_1 + 32'd1}; - 3: ; - 2: reg_3 <= reg_2; - 1: reg_10 = 32'd1; -reg_11 = reg_3; + 4: reg_2 <= 32'd3; + 3: reg_6[32'd0] <= reg_2; + 2: reg_1 <= reg_6[32'd0]; + 1: reg_4 = 32'd1; +reg_5 = reg_1; } controllogic { - 15: reg_9 <= 32'd14; - 14: reg_9 <= 32'd13; - 13: reg_9 <= 32'd12; - 12: reg_9 <= 32'd11; - 11: reg_9 <= 32'd10; - 10: reg_9 <= 32'd9; - 9: reg_9 <= 32'd8; - 8: reg_9 <= 32'd7; - 7: reg_9 <= 32'd6; - 6: reg_9 <= 32'd5; - 5: reg_9 <= 32'd4; - 4: reg_9 <= 32'd3; - 3: reg_9 <= ({$signed(reg_1) < $signed(32'd3)} ? 32'd7 : 32'd2); - 2: reg_9 <= 32'd1; + 4: reg_3 <= 32'd3; + 3: reg_3 <= 32'd2; + 2: reg_3 <= 32'd1; 1: ; } } diff --git a/data/accumulator.rtl b/data/accumulator.rtl index bf0af2f..388965c 100644 --- a/data/accumulator.rtl +++ b/data/accumulator.rtl @@ -1,18 +1,6 @@ main() { -6: x9 = 1 -5: int32[stack(0)] = x9 -4: x8 = 2 -3: int32[stack(4)] = x8 -2: x7 = 3 -1: int32[stack(8)] = x7 -0: x3 = 0 -9: nop -8: x1 = 0 -7: x6 = stack(0) (int) -6: x5 = int32[x6 + x1 * 4 + 0] -5: x3 = x3 + x5 + 0 (int) -4: x1 = x1 + 1 (int) -3: if (x1 <s 3) goto 7 else goto 2 -2: x4 = x3 -1: return x4 + x2 = 3 + int32[stack(0)] = x2 + x1 = int32[stack(0)] + return x1 } diff --git a/data/accumulator.v b/data/accumulator.v index 799756f..aaed3da 100644 --- a/data/accumulator.v +++ b/data/accumulator.v @@ -1,145 +1,46 @@ -module main(reg_13, reg_14, reg_15, reg_10, reg_11); - always @(posedge reg_15) - if ({reg_14 == 32'd1}) begin - reg_9 <= 32'd15; - end else begin - case (reg_9) - 32'd8: begin - reg_9 <= 32'd7; - end - 32'd4: begin - reg_9 <= 32'd3; - end - 32'd12: begin - reg_9 <= 32'd11; - end - 32'd2: begin - reg_9 <= 32'd1; - end - 32'd10: begin - reg_9 <= 32'd9; - end - 32'd6: begin - reg_9 <= 32'd5; - end - 32'd14: begin - reg_9 <= 32'd13; - end - 32'd1: begin - ; - end - 32'd9: begin - reg_9 <= 32'd8; - end - 32'd5: begin - reg_9 <= 32'd4; - end - 32'd13: begin - reg_9 <= 32'd12; - end - 32'd3: begin - reg_9 <= ({$signed(reg_1) < $signed(32'd3)} ? 32'd7 : 32'd2); - end - 32'd11: begin - reg_9 <= 32'd10; - end - 32'd7: begin - reg_9 <= 32'd6; - end - 32'd15: begin - reg_9 <= 32'd14; - end - default:; - endcase +module main(reset, clk, finish, return_val); + input [0:0] clk, reset; + output reg [31:0] return_val = 0; + output reg [0:0] finish = 0; + reg [0:0] en = 0, wr_en = 0, u_en = 0; + reg [31:0] state = 0, d_out = 0, d_in = 0; + reg [31:0] reg_1 = 0, addr = 0, reg_2 = 0; + reg [31:0] stack [0:0]; + always @(negedge clk) + if ({u_en != en}) begin + if (wr_en) stack[addr] <= d_in; + else d_out <= stack[addr]; + en <= u_en; end - always @(posedge reg_15) - case (reg_9) - 32'd8: begin - reg_1 <= 32'd0; - end - 32'd4: begin - reg_1 <= {reg_1 + 32'd1}; - end - 32'd12: begin - reg_12[32'd1] <= reg_7; + always @(posedge clk) + case (state) + 32'd6: reg_1 <= d_out; + 32'd4: reg_2 <= 32'd3; + 32'd3: begin + u_en <= ( ! u_en); + wr_en <= 32'd1; + d_in <= reg_2; + addr <= 32'd0; end 32'd2: begin - reg_3 <= reg_2; - end - 32'd10: begin - reg_12[32'd2] <= reg_6; - end - 32'd6: begin - reg_4 <= reg_12[{{{reg_5 + 32'd0} + {reg_1 * 32'd4}} / 32'd4}]; - end - 32'd14: begin - reg_12[32'd0] <= reg_8; + u_en <= ( ! u_en); + wr_en <= 32'd0; + addr <= 32'd0; end 32'd1: begin - reg_10 = 32'd1; - reg_11 = reg_3; - end - 32'd9: begin - reg_2 <= 32'd0; - end - 32'd5: begin - reg_2 <= {{reg_2 + reg_4} + 32'd0}; - end - 32'd13: begin - reg_7 <= 32'd2; - end - 32'd3: begin - ; - end - 32'd11: begin - reg_6 <= 32'd3; - end - 32'd7: begin - reg_5 <= 32'd0; - end - 32'd15: begin - reg_8 <= 32'd1; + finish = 32'd1; + return_val = reg_1; end default:; endcase - reg [31:0] reg_12 [2:0]; - reg [31:0] reg_8; - reg [31:0] reg_4; - reg [31:0] reg_2; - output reg [0:0] reg_10; - reg [31:0] reg_6; - input [0:0] reg_14; - reg [31:0] reg_1; - reg [31:0] reg_9; - reg [31:0] reg_5; - input [0:0] reg_13; - reg [31:0] reg_3; - output reg [31:0] reg_11; - reg [31:0] reg_7; - input [0:0] reg_15; -endmodule - -module testbench; - reg start, reset, clk; - wire finish; - wire [31:0] return_val; - - main m(start, reset, clk, finish, return_val); - - initial begin - clk = 0; - start = 0; - reset = 0; - @(posedge clk) reset = 1; - @(posedge clk) reset = 0; - end - - always #5 clk = ~clk; - - always @(posedge clk) begin - if (finish == 1) begin - $display("finished: %d", return_val); - $finish; - end - end + always @(posedge clk) + if ({reset == 32'd1}) state <= 32'd4; + else case (state) + 32'd6: state <= 32'd1; + 32'd4: state <= 32'd3; + 32'd3: state <= 32'd2; + 32'd2: state <= 32'd6; + 32'd1: ; + default:; + endcase endmodule |