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authorYann Herklotz <git@yannherklotz.com>2020-06-30 10:20:44 +0100
committerYann Herklotz <git@yannherklotz.com>2020-06-30 10:20:44 +0100
commit1936da65bc9bbfe847c1ff2b7abadff5bdc14f8f (patch)
tree22e7b24fc1bf2ffac9a65b1836b60e419f3e218a /main.tex
parentaf9e95f99d412e3c113ce93ed22bf2e67f4b5202 (diff)
downloadoopsla21_fvhls-1936da65bc9bbfe847c1ff2b7abadff5bdc14f8f.tar.gz
oopsla21_fvhls-1936da65bc9bbfe847c1ff2b7abadff5bdc14f8f.zip
Add modifications to Verilog syntax adn implement more notes
Diffstat (limited to 'main.tex')
-rw-r--r--main.tex2
1 files changed, 1 insertions, 1 deletions
diff --git a/main.tex b/main.tex
index 40151be..7a168ca 100644
--- a/main.tex
+++ b/main.tex
@@ -182,8 +182,8 @@
\maketitle
\input{introduction}
-\input{verilog}
\input{algorithm}
+\input{verilog}
\input{proof}
\input{evaluation}
\input{related}