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| author | Yann Herklotz <git@yannherklotz.com> | 2020-11-05 08:46:00 +0000 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2020-11-05 08:46:00 +0000 |
| commit | 47451890bb20e3174b5821ecdebce17ef3031fd0 (patch) | |
| tree | 87458a35a5f6aa437b6a6714cd5b9fedee924e61 /references.bib | |
| parent | b40700a836a7e47044b456d364d4fa846bfcb2de (diff) | |
| download | oopsla21_fvhls-47451890bb20e3174b5821ecdebce17ef3031fd0.tar.gz oopsla21_fvhls-47451890bb20e3174b5821ecdebce17ef3031fd0.zip | |
Update references
Diffstat (limited to 'references.bib')
| -rw-r--r-- | references.bib | 56 |
1 files changed, 30 insertions, 26 deletions
diff --git a/references.bib b/references.bib index 9c18163..78a317a 100644 --- a/references.bib +++ b/references.bib @@ -335,19 +335,6 @@ year = {2008}, } -@article{06_ieee_stand_veril_hardw_descr_languag, - author = {}, - title = {IEEE Standard for Verilog Hardware Description Language}, - journal = {IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)}, - volume = {}, - number = {}, - pages = {1-590}, - year = {2006}, - doi = {10.1109/IEEESTD.2006.99495}, - ISSN = {}, - month = {April}, -} - @inproceedings{loow19_verif_compil_verif_proces, author = {L\"{o}\"{o}w, Andreas and Kumar, Ramana and Tan, Yong Kiam and Myreen, Magnus O. and Norrish, Michael and Abrahamsson, Oskar @@ -418,17 +405,34 @@ isbn = 0070163332, } -@techreport{05_veril_regis_trans_level_synth, - type = {Standard}, - key = {IEEE Std 1364.1}, - title = {{IEEE} Standard for {Verilog} Register Transfer Level Synthesis}, - journal = {IEC 62142-2005 First edition 2005-06 IEEE Std 1364.1}, - volume = {}, - number = {}, - pages = {1-116}, - year = {2005}, - doi = {10.1109/IEEESTD.2005.339572}, - ISSN = {}, - keywords = {IEC Standards;Verilog;Registers}, - month = {}, +@article{05_ieee_stand_veril_regis_trans_level_synth, + title = {{IEEE} Standard for {Verilog} Register Transfer Level Synthesis}, + journal = {IEC 62142-2005 First edition 2005-06 IEEE Std 1364.1}, + volume = {}, + number = {}, + pages = {1-116}, + year = {2005}, + doi = {10.1109/IEEESTD.2005.339572}, + url = {https://doi.org/10.1109/IEEESTD.2005.339572}, + ISSN = {}, + key = {IEEE Std 1364.1}, + keywords = {IEC Standards;Verilog;Registers}, + month = {}, + type = {Standard}, +} + +@article{06_ieee_stand_veril_hardw_descr_languag, + author = {}, + title = {{IEEE} Standard for Verilog Hardware Description Language}, + journal = {IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)}, + volume = {}, + number = {}, + pages = {1-590}, + year = {2006}, + doi = {10.1109/IEEESTD.2006.99495}, + url = {https://doi.org/10.1109/IEEESTD.2006.99495}, + ISSN = {}, + key = {IEEE Std 1364}, + month = {April}, + type = {Standard}, } |