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| author | Yann Herklotz <git@yannherklotz.com> | 2020-10-21 10:58:33 +0100 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2020-10-21 10:58:33 +0100 |
| commit | 6dd9605a5e83d0539bcdefeca675f1070038ee68 (patch) | |
| tree | c02efeafcf5dde612e598b9799a12576a4bd68f9 /references.bib | |
| parent | f16ba021e4f5c7f5a933acbd7e38e077bbb42d75 (diff) | |
| download | oopsla21_fvhls-6dd9605a5e83d0539bcdefeca675f1070038ee68.tar.gz oopsla21_fvhls-6dd9605a5e83d0539bcdefeca675f1070038ee68.zip | |
Work on Nadesh's comments in Verilog section
Diffstat (limited to 'references.bib')
| -rw-r--r-- | references.bib | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/references.bib b/references.bib index ee57c3b..9c18163 100644 --- a/references.bib +++ b/references.bib @@ -417,3 +417,18 @@ edition = {1st}, isbn = 0070163332, } + +@techreport{05_veril_regis_trans_level_synth, + type = {Standard}, + key = {IEEE Std 1364.1}, + title = {{IEEE} Standard for {Verilog} Register Transfer Level Synthesis}, + journal = {IEC 62142-2005 First edition 2005-06 IEEE Std 1364.1}, + volume = {}, + number = {}, + pages = {1-116}, + year = {2005}, + doi = {10.1109/IEEESTD.2005.339572}, + ISSN = {}, + keywords = {IEC Standards;Verilog;Registers}, + month = {}, +} |