Add diagrams

1 files changed, 20 insertions, 0 deletions

diff --git a/verilog.tex b/verilog.tex
index cf5b455..dbcf0e1 100644
--- a/verilog.tex
+++ b/verilog.tex
@@ -109,6 +109,26 @@ Therefore, in addition to the rules shown in Figure~\ref{fig:inferrence_module},
 
 \noindent where the initial state is the \texttt{Callstate} with an empty stack frame and no arguments for the \texttt{main} function of program $P$, where this \texttt{main} function needs to be in the current translation unit.  The final state results in the program output of value $n$ when reaching a \texttt{Returnstate} with an empty stack frame.
 
+\subsection{Memory Model}
+
+\begin{figure}
+  \centering
+  \begin{subfigure}[t]{0.48\linewidth}
+    \includegraphics[width=\linewidth]{diagrams/store_waveform.pdf}
+    \caption{Store waveform.}
+  \end{subfigure}\hfill%
+  \begin{subfigure}[t]{0.48\linewidth}
+    \includegraphics[width=\linewidth]{diagrams/load_waveform.pdf}
+    \caption{Load waveform.}
+  \end{subfigure}
+\end{figure}
+
+\begin{figure}
+  \centering
+  \includegraphics[width=0.5\linewidth]{diagrams/memory_model.pdf}
+  \caption{Change in the memory model during the translation of 3AC to HTL.}
+\end{figure}
+
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