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diff --git a/chapters/pipelining.tex b/chapters/pipelining.tex index 5e07bd7..9bdacc1 100644 --- a/chapters/pipelining.tex +++ b/chapters/pipelining.tex @@ -5,4 +5,19 @@ \chapter[sec:pipelining]{Loop Pipelining} +\startsynopsis + This section describes the future plans of implementing loop pipelining in Vericert, also called + loop scheduling. This addresses the final major issue with Vericert, which is efficiently + handling loops. +\stopsynopsis + +Standard instruction scheduling only addresses parallelisation inside hyperblocks, which are linear +sections of code. However, loops are often the most critical sections in code, and scheduling only +addresses parallelisation within one iteration. + +\section{Introduction to loop pipelining} + +\section{Bibliography} +\placelistofpublications + \stopcomponent |