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| author | James Pollard <james@pollard.dev> | 2020-06-12 17:48:51 +0100 |
|---|---|---|
| committer | James Pollard <james@pollard.dev> | 2020-06-12 17:48:51 +0100 |
| commit | f7795011ea9ac0d34ee565d3832f15b649bf1827 (patch) | |
| tree | fd731b58626c8665032afd62068ece8cedc76eb0 /src/verilog/HTL.v | |
| parent | 9acb804500b590edbff66cd802216f58dde169cd (diff) | |
| parent | 86f42b92d87020875e2a7ef4ba40de12d261685f (diff) | |
| download | vericert-kvx-f7795011ea9ac0d34ee565d3832f15b649bf1827.tar.gz vericert-kvx-f7795011ea9ac0d34ee565d3832f15b649bf1827.zip | |
Merge branch 'master' into arrays-proof
Diffstat (limited to 'src/verilog/HTL.v')
| -rw-r--r-- | src/verilog/HTL.v | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/verilog/HTL.v b/src/verilog/HTL.v index 82aac41..c509248 100644 --- a/src/verilog/HTL.v +++ b/src/verilog/HTL.v @@ -48,7 +48,12 @@ Record module: Type := mod_stk : reg; mod_stk_len : nat; mod_finish : reg; - mod_return : reg + mod_return : reg; + mod_start : reg; + mod_reset : reg; + mod_clk : reg; + mod_scldecls : AssocMap.t (option Verilog.io * Verilog.scl_decl); + mod_arrdecls : AssocMap.t (option Verilog.io * Verilog.arr_decl); }. Definition fundef := AST.fundef module. |