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| author | Yann Herklotz <git@yannherklotz.com> | 2020-06-14 14:12:38 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-06-14 14:12:38 +0100 |
| commit | a23cc48f449ffbfd347f833965c1e04b88e0009a (patch) | |
| tree | a2f052d935a9db4fe34ca518a4bc81ad0ae6fd30 /src/verilog/PrintVerilog.ml | |
| parent | 8e3c89bad3a20c0bb9c88b83d966565d79822ff1 (diff) | |
| download | vericert-kvx-a23cc48f449ffbfd347f833965c1e04b88e0009a.tar.gz vericert-kvx-a23cc48f449ffbfd347f833965c1e04b88e0009a.zip | |
Add more unproven instructions, Admitted equiv to spec
Diffstat (limited to 'src/verilog/PrintVerilog.ml')
| -rw-r--r-- | src/verilog/PrintVerilog.ml | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml index 700b8e3..a0f3ab3 100644 --- a/src/verilog/PrintVerilog.ml +++ b/src/verilog/PrintVerilog.ml @@ -58,7 +58,8 @@ let pprint_binop l r = | Vor -> unsigned "|" | Vxor -> unsigned "^" | Vshl -> unsigned "<<" - | Vshr -> unsigned ">>" + | Vshr -> signed ">>>" + | Vshru -> unsigned ">>" let unop = function | Vneg -> " ~ " |