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Diffstat (limited to 'src/verilog/PrintVerilog.mli')
| -rw-r--r-- | src/verilog/PrintVerilog.mli | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli index 181a9d2..b4d2937 100644 --- a/src/verilog/PrintVerilog.mli +++ b/src/verilog/PrintVerilog.mli @@ -17,3 +17,5 @@ *) val print_program : out_channel -> Verilog.coq_module -> unit + +val print_result : (BinNums.positive * Value.value) list -> unit |