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vericert-kvx
arrays-proof
dev-experiments
dev-initial
dev-initial-blocks
dev-michalis
dev-nadesh
dev-nadesh-merge
dev-nadesh-proven
dev/cond-const-prop
dev/div
dev/divider
dev/improved-names
dev/io
dev/predicated-execution
dev/scheduling
dev/value
exp/inl-cse-const
master
michalis
michalis-merge
michalis_merge_2
mpardalos-michalis
oopsla21
save/old-step
wip/reset-signals
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Veriloggen.v
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Author
Age
Files
Lines
*
Change name to Vericert
Yann Herklotz
2020-07-14
1
-2
/
+2
*
Remove admitted in mis_stepp_Vdecl
Yann Herklotz
2020-07-05
1
-3
/
+3
*
Finish most of Veriloggenproof
Yann Herklotz
2020-07-05
1
-18
/
+16
*
Fix Verilog semantics and fix order of always blocks
Yann Herklotz
2020-06-26
1
-2
/
+2
*
Array semantics now uses dependent Array type.
James Pollard
2020-06-14
1
-2
/
+3
*
Generate Verilog from HTL
Yann Herklotz
2020-06-12
1
-644
/
+40
*
Merge branch 'develop' into arrays-proof
James Pollard
2020-05-30
1
-20
/
+51
|
\
|
*
Add equality check for value
Yann Herklotz
2020-05-04
1
-1
/
+1
|
*
Add state transition conversion functions
Yann Herklotz
2020-05-03
1
-2
/
+14
|
*
Add documentation and conform to specification
Yann Herklotz
2020-04-29
1
-24
/
+41
*
|
Stop using tuples for register declarations
James Pollard
2020-05-30
1
-37
/
+39
*
|
Fix addressing to add support for arbitraty pointer operations
James Pollard
2020-05-27
1
-10
/
+19
*
|
Bug fix: stack address normalisation
James Pollard
2020-05-26
1
-1
/
+1
*
|
(Tentatively) working stack array/memory support.
James Pollard
2020-05-26
1
-37
/
+50
*
|
Add pattern matches and plumb through stack reg
James Pollard
2020-05-25
1
-5
/
+21
*
|
Start work on array support
James Pollard
2020-05-25
1
-0
/
+1
|
/
*
Only generate clocked always blocks
Yann Herklotz
2020-04-17
1
-13
/
+13
*
Make proofs simpler using auto
Yann Herklotz
2020-04-15
1
-59
/
+45
*
Add proof about state wf
Yann Herklotz
2020-04-08
1
-40
/
+193
*
Add partial proof of well formed state
Yann Herklotz
2020-04-06
1
-24
/
+136
*
Handle loops and conditionals correctly
Yann Herklotz
2020-04-02
1
-100
/
+128
*
Complete translation from simple RTL to Verilog
Yann Herklotz
2020-04-01
1
-101
/
+162
*
Convert from RTL to Verilog directly
Yann Herklotz
2020-03-31
1
-18
/
+20
*
Add more operators and print them
Yann Herklotz
2020-03-31
1
-37
/
+69
*
Improve Verilog error messages
Yann Herklotz
2020-03-31
1
-1
/
+7
*
Rename to transf_program
Yann Herklotz
2020-03-29
1
-1
/
+1
*
Complete conversion from HTL to Verilog
Yann Herklotz
2020-03-29
1
-8
/
+91
*
Add Verilog generation from HTL
Yann Herklotz
2020-03-29
1
-0
/
+135