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| author | Yann Herklotz <git@yannherklotz.com> | 2023-08-10 11:17:19 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2023-08-10 11:17:19 +0100 |
| commit | b32e7574864cde80f8f5283431c21a6803a89108 (patch) | |
| tree | f30babb0db7e5797cb77f6ac44a682cb9b8b105b /scripts/synth.tcl | |
| parent | c321e39de166308d8db2f6ebe577edb3297b507c (diff) | |
| download | vericert-b32e7574864cde80f8f5283431c21a6803a89108.tar.gz vericert-b32e7574864cde80f8f5283431c21a6803a89108.zip | |
Fix backend hardware generation and scheduling
Diffstat (limited to 'scripts/synth.tcl')
| -rw-r--r-- | scripts/synth.tcl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/scripts/synth.tcl b/scripts/synth.tcl index a2fb722..f5a2388 100644 --- a/scripts/synth.tcl +++ b/scripts/synth.tcl @@ -76,7 +76,7 @@ proc dump_statistics { } { }; #END PROC set outputDir . create_project -in_memory -part xc7z020clg484-1 -force -read_verilog -sv main.v +read_verilog -sv main.sv synth_design -mode out_of_context -no_iobuf -top main -part xc7z020clg484-1 write_checkpoint -force $outputDir/post_synth.dcp report_timing_summary -file $outputDir/post_synth_timing_summary.rpt |