aboutsummaryrefslogtreecommitdiffstats
path: root/scripts
diff options
context:
space:
mode:
authorYann Herklotz <git@yannherklotz.com>2022-03-19 12:05:44 +0000
committerYann Herklotz <git@yannherklotz.com>2022-03-22 16:18:06 +0000
commit27fea2fe14a81f4e73e0e3e53ec5ac5db07a5d82 (patch)
tree4c474f1426a0f84f131300eff3c70f43cf7f77bc /scripts
parent23fe30f8c23ecb743880cb9239410eb51bf1abab (diff)
downloadvericert-27fea2fe14a81f4e73e0e3e53ec5ac5db07a5d82.tar.gz
vericert-27fea2fe14a81f4e73e0e3e53ec5ac5db07a5d82.zip
Delete extra data files and scripts
Diffstat (limited to 'scripts')
-rw-r--r--scripts/quartus_synth.tcl35
-rwxr-xr-xscripts/run-vericert.sh46
-rw-r--r--scripts/script.R29
-rwxr-xr-xscripts/syn-remote.sh51
-rwxr-xr-xscripts/synthesis-results.scm5
5 files changed, 163 insertions, 3 deletions
diff --git a/scripts/quartus_synth.tcl b/scripts/quartus_synth.tcl
new file mode 100644
index 0000000..6edbf0c
--- /dev/null
+++ b/scripts/quartus_synth.tcl
@@ -0,0 +1,35 @@
+# PRiME pre-KAPow kernel flow
+# Performs pre-KAPow run steps for instrumenting arbitrary Verilog for power monitoring
+# James Davis, 2015
+
+load_package flow
+
+project_new -overwrite syn
+set_global_assignment -name FAMILY "Arria 10"
+set_global_assignment -name DEVICE 10AX115H4F34E3LG
+set_global_assignment -name SYSTEMVERILOG_FILE top.v
+set_global_assignment -name TOP_LEVEL_ENTITY main
+#set_global_assignment -name SDC_FILE syn.sdc
+#set_global_assignment -name auto_resource_sharing on
+#set_global_assignment -name enable_state_machine_inference on
+#set_global_assignment -name optimization_technique area
+#set_global_assignment -name synthesis_effort fast
+#set_global_assignment -name AUTO_RAM_RECOGNITION on
+#set_global_assignment -name remove_duplicate_registers on
+#set_instance_assignment -name RAMSTYLE_ATTRIBUTE LOGIC -to ram
+
+execute_module -tool map
+
+execute_module -tool fit
+
+execute_module -tool sta
+
+#execute_module -tool eda -args "--simulation --tool=vcs"
+
+# set_global_assignment -name POWER_OUTPUT_SAF_NAME ${kernel}.asf
+# set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
+# set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY ON
+# set_global_assignment -name POWER_REPORT_POWER_DISSIPATION ON
+# execute_module -tool pow
+
+project_close
diff --git a/scripts/run-vericert.sh b/scripts/run-vericert.sh
new file mode 100755
index 0000000..9deaa10
--- /dev/null
+++ b/scripts/run-vericert.sh
@@ -0,0 +1,46 @@
+#!/usr/bin/env bash
+
+rm exec.csv
+
+top=$(pwd)
+#set up
+while read benchmark ; do
+ printf "%10s\t" $(echo "$benchmark" | sed -e 's|/| |g')
+ ./$benchmark.gcc > $benchmark.clog
+ cresult=$(cat $benchmark.clog | cut -d' ' -f2)
+ #echo "C output: "$cresult
+ #./$benchmark.iver > $benchmark.tmp
+ if [[ ! -f ./$benchmark.verilator/Vmain ]]; then
+ echo -e "\e[0;91mFAIL\e[0m: Verilog failed compilation"
+ continue
+ fi
+ ./$benchmark.verilator/Vmain > $benchmark.tmp
+ veriresult=$(tail -1 $benchmark.tmp | cut -d' ' -f2)
+ cycles=$(tail -2 $benchmark.tmp | head -1 | tr -s ' ' | cut -d' ' -f2)
+ #echo "Verilog output: "$veriresult
+
+ #Undefined checks
+ if [[ -z "$veriresult" ]]
+ then
+ echo "\e[0;91mFAIL\e[0m: Verilog returned nothing"
+ #exit 0
+ fi
+
+ # Don't care checks
+ if [[ $veriresult == "x" ]]
+ then
+ echo "\e[0;91mFAIL\e[0m: Verilog returned don't cares"
+ #exit 0
+ fi
+
+ # unequal result check
+ if [[ $cresult -ne $veriresult ]]
+ then
+ echo -e "\e[0;91mFAIL\e[0m: Verilog and C output do not match!"
+ #exit 0
+ else
+ echo -e "\e[0;92mPASS\e[0m"
+ fi
+ name=$(echo $benchmark | awk -v FS="/" '{print $NF}')
+ echo $name","$cycles >> exec.csv
+done < benchmark-list-master
diff --git a/scripts/script.R b/scripts/script.R
new file mode 100644
index 0000000..0be16da
--- /dev/null
+++ b/scripts/script.R
@@ -0,0 +1,29 @@
+library("psych")
+
+data = read.csv("poly.csv", header=TRUE)
+leguptime = (data$legupcycles/data$legupfreqMHz)
+veritime = data$vericertcycles/data$vericertfreqMHz
+print(lm(veritime ~ leguptime))
+leguputil = data$leguplogicutilisation/427200*100
+veriutil = data$vericertlogicutilisation/427200*100
+print(lm (veriutil ~ leguputil))
+legupct = data$legupcomptime
+verict = data$vericertcomptime
+print(lm ( verict ~ legupct ))
+
+cycleslowdown=data$vericertcycles/data$legupcycles
+
+print("Cycle count slow down")
+print(geometric.mean(cycleslowdown))
+print("Wall clock slow down")
+print(geometric.mean(veritime/leguptime))
+print("Area overhead")
+print(geometric.mean(veriutil/leguputil))
+print("Compilation time speedup")
+print(geometric.mean(legupct/verict))
+print("LegUp RAM use")
+print(geometric.mean(data$legupregs))
+print("Vericert RAM use")
+print(geometric.mean(data$vericertregs))
+print("Area overhead")
+print(geometric.mean(data$vericertregs/data$legupregs))
diff --git a/scripts/syn-remote.sh b/scripts/syn-remote.sh
new file mode 100755
index 0000000..879db2e
--- /dev/null
+++ b/scripts/syn-remote.sh
@@ -0,0 +1,51 @@
+#! /bin/bash
+
+#setup
+while read benchmark ;
+do
+echo "Setting up "$benchmark
+rm -r $benchmark
+mkdir $benchmark
+cp $benchmark.v $benchmark/top.v
+
+done < syn-list
+
+#synthesis
+
+count=0
+while read benchmark ;
+
+do
+echo "Synthesising "$benchmark
+cd $benchmark
+quartus_sh -t ../quartus_synth.tcl &
+let "count=count+1"
+cd ..
+
+if [ $count -eq 4 ]
+then
+echo "I am here"
+wait
+count=0
+fi
+
+done < syn-list
+
+if [ $count -lt 4 ]
+then
+wait
+fi
+
+#extract
+while read benchmark ; do
+ cd $benchmark
+ echo $(pwd)
+ freq=$(grep MHz syn.sta.rpt | tail -2 | head -1 | awk '{print $2}')
+ lut=$(sed -n -e 8p syn.fit.summary | awk '{print $6}' | sed 's/,//g')
+ regs=$(sed -n -e 9p syn.fit.summary | awk '{print $4}')
+ bram=$(sed -n -e 13p syn.fit.summary | awk '{print $5}')
+ dsp=$(sed -n -e 14p syn.fit.summary | awk '{print $5}')
+ cd ..
+ echo $benchmark","$freq","$lut","$regs","$bram","$dsp >> results
+done < syn-list
+
diff --git a/scripts/synthesis-results.scm b/scripts/synthesis-results.scm
index 11c66c1..94c169f 100755
--- a/scripts/synthesis-results.scm
+++ b/scripts/synthesis-results.scm
@@ -91,7 +91,7 @@
(lambda ()
(list name (xml-matcher (ssax:xml->sxml (current-input-port) '()))))))
-(define (to-csv-record b head results)
+(define ((to-csv-record b head) results)
(let ((res (map (lambda (key)
(cadr (assoc key (cadr results)))) head)))
(csv:fmt-row (if b res (cons (car results) res)))))
@@ -126,8 +126,7 @@
(let ((head (split-at-comma (or (check-opt 'keys) "slice,ramfifo,delay")))
(suppress (split-at-comma (or (check-opt 'suppress) "none")))
(files (get-files-from-op operands)))
- (let ((body (map (lambda (f) (to-csv-record (member "name" suppress) head f))
- (convert-files files)))
+ (let ((body (map (to-csv-record (member "name" suppress) head) (convert-files files)))
(header (csv:fmt-row (if (member "name" suppress) head (cons "name" head)))))
(with-output
(lambda ()