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| author | Yann Herklotz <git@yannherklotz.com> | 2020-06-12 11:37:22 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-06-12 11:37:22 +0100 |
| commit | f470234beafacccf743a75d4d0e6213b8861ca30 (patch) | |
| tree | 8378e7d908afb6b609e1d0121900455177d211e9 /src/extraction | |
| parent | 1ceb1a28f0e08406862f03863c5d00639ada147d (diff) | |
| download | vericert-f470234beafacccf743a75d4d0e6213b8861ca30.tar.gz vericert-f470234beafacccf743a75d4d0e6213b8861ca30.zip | |
Remove extraction of simulator
Diffstat (limited to 'src/extraction')
| -rw-r--r-- | src/extraction/Extraction.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index 0028fcb..ba87af6 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -16,7 +16,7 @@ * along with this program. If not, see <https://www.gnu.org/licenses/>. *) -From coqup Require Verilog Value Compiler Simulator. +From coqup Require Verilog Value Compiler. From Coq Require DecidableClass. @@ -166,7 +166,7 @@ Set Extraction AccessOpaque. Cd "src/extraction". Separate Extraction - Verilog.module Value.uvalueToZ coqup.Compiler.transf_hls Simulator.simulate + Verilog.module Value.uvalueToZ coqup.Compiler.transf_hls Compiler.transf_c_program Compiler.transf_cminor_program Cexec.do_initial_state Cexec.do_step Cexec.at_final_state |