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author | Yann Herklotz <git@yannherklotz.com> | 2020-07-24 10:22:13 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-07-24 10:22:13 +0100 |
commit | 5cf10a4c70763cbb95747b19ac35b57a9dee4dd5 (patch) | |
tree | eeb5a90e4d651093ac27058d4e83775a37ae1348 /src/verilog/PrintVerilog.mli | |
parent | 1cc5a458f28ad44919c9bfafbd5191c253e453e2 (diff) | |
download | vericert-5cf10a4c70763cbb95747b19ac35b57a9dee4dd5.tar.gz vericert-5cf10a4c70763cbb95747b19ac35b57a9dee4dd5.zip |
More renames to get it to compile
Diffstat (limited to 'src/verilog/PrintVerilog.mli')
-rw-r--r-- | src/verilog/PrintVerilog.mli | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli index 47af3ef..6a15ee9 100644 --- a/src/verilog/PrintVerilog.mli +++ b/src/verilog/PrintVerilog.mli @@ -18,8 +18,8 @@ val pprint_stmnt : int -> Verilog.stmnt -> string -val print_value : out_channel -> Value.value -> unit +val print_value : out_channel -> ValueInt.value -> unit val print_program : bool -> out_channel -> Verilog.program -> unit -val print_result : out_channel -> (BinNums.positive * Value.value) list -> unit +val print_result : out_channel -> (BinNums.positive * ValueInt.value) list -> unit |