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| author | Michalis Pardalos <m.pardalos@gmail.com> | 2021-02-28 22:00:57 +0000 |
|---|---|---|
| committer | Michalis Pardalos <m.pardalos@gmail.com> | 2021-02-28 22:00:57 +0000 |
| commit | ef205f12c75891be73d221995946df441d143791 (patch) | |
| tree | 0b02f65f81b75b254c5ca2b3536ee1c2ac34959d /src | |
| parent | a8d8d518a25e0f62f089344c6a888daf9f301958 (diff) | |
| download | vericert-ef205f12c75891be73d221995946df441d143791.tar.gz vericert-ef205f12c75891be73d221995946df441d143791.zip | |
Unset finish signal on reset
Diffstat (limited to 'src')
| -rw-r--r-- | src/hls/Veriloggen.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/hls/Veriloggen.v b/src/hls/Veriloggen.v index a7a8c2a..83f7abe 100644 --- a/src/hls/Veriloggen.v +++ b/src/hls/Veriloggen.v @@ -337,7 +337,9 @@ Section TRANSLATE. let body : list Verilog.module_item:= Valways (Vposedge (HTL.mod_clk m)) (Vcond (Vbinop Veq (Vvar (HTL.mod_reset m)) (Vlit (ZToValue 1))) - (Vnonblock (Vvar (HTL.mod_st m)) (Vlit (posToValue (HTL.mod_entrypoint m)))) + (Vseq + (Vnonblock (Vvar (HTL.mod_st m)) (Vlit (posToValue (HTL.mod_entrypoint m)))) + (Vnonblock (Vvar (HTL.mod_finish m)) (Vlit (ZToValue 0)))) (Vcase (Vvar (HTL.mod_st m)) case_el_ctrl (Some Vskip))) :: Valways (Vposedge (HTL.mod_clk m)) (Vcase (Vvar (HTL.mod_st m)) case_el_data (Some Vskip)) :: List.map Vdeclaration (arr_to_Vdeclarr (AssocMap.elements (HTL.mod_arrdecls m)) |