| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [WIP] Generate calling verilog in RTL->HTL | Michalis Pardalos | 2021-04-18 | 1 | -0/+8 |
| * | Add correct copyright notices in files | Yann Herklotz | 2021-01-10 | 1 | -0/+18 |
| * | Change name to Vericert | Yann Herklotz | 2020-07-14 | 1 | -1/+1 |
| * | Add statemonad declaration | Yann Herklotz | 2020-05-24 | 1 | -0/+61 |
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index : vericert | |
| Vericert is a formally verified high-level synthesis tool. |
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