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| author | Yann Herklotz <git@yannherklotz.com> | 2019-06-05 13:26:47 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-06-05 13:26:47 +0100 |
| commit | f3268d934a9a2b01633b5f7a3353d1a97c40a9df (patch) | |
| tree | fc2cd0b891cf47bb8f36b782af8c8671331a45ce | |
| parent | c40faa081ae7f31cb1b6125d1c5c3bdf650f3f63 (diff) | |
| download | verismith-f3268d934a9a2b01633b5f7a3353d1a97c40a9df.tar.gz verismith-f3268d934a9a2b01633b5f7a3353d1a97c40a9df.zip | |
Fix size in output wire
| -rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index cb3a8ad..c8860ce 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -464,9 +464,10 @@ moduleDef top = do $ local ^.. traverse . portSize + let combine = config ^. configProperty . propCombine let clock = Port Wire False 1 "clk" - let yport = if True then Port Wire False 1 "y" else Port Wire False size "y" - let comb = combineAssigns_ (config ^. configProperty . propCombine) yport local + let yport = if combine then Port Wire False 1 "y" else Port Wire False size "y" + let comb = combineAssigns_ combine yport local return . declareMod local . ModDecl name [yport] (clock : portList) (comb : mi) |