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| author | Yann Herklotz <git@yannherklotz.com> | 2019-06-02 13:25:37 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-06-02 13:25:37 +0100 |
| commit | f4dbd5a813de78a9241573a498a9bb1cb40c65f3 (patch) | |
| tree | f4a5392eca6b8a0fe057c38c5a0462cd60a51532 | |
| parent | 74f410dc07afe2d0a07f61a1dfa85c15cc31e446 (diff) | |
| download | verismith-f4dbd5a813de78a9241573a498a9bb1cb40c65f3.tar.gz verismith-f4dbd5a813de78a9241573a498a9bb1cb40c65f3.zip | |
Remove dead code
| -rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index 828224f..c903e28 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -464,7 +464,7 @@ moduleDef top = do ^.. traverse . portSize let clock = Port Wire False 1 "clk" - let yport = Port Wire False 1 "y" + let yport = if True then Port Wire False 1 "y" else Port Wire False size "y" let comb = combineAssigns_ yport local return . declareMod local |