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| author | Yann Herklotz <git@yannherklotz.com> | 2019-11-24 18:00:01 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-11-24 18:00:01 +0000 |
| commit | 425fbf1f675cfd47265999cc522bf1121a43efb1 (patch) | |
| tree | aa5b8a594e80864c168816007c75ba84b0efb1f2 | |
| parent | 6ceb00347d5759e739cffb2f731392869b8fe42e (diff) | |
| download | verismith-425fbf1f675cfd47265999cc522bf1121a43efb1.tar.gz verismith-425fbf1f675cfd47265999cc522bf1121a43efb1.zip | |
Add ModConnNamed in testbench
| -rw-r--r-- | src/Verismith/Verilog/Mutate.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Verismith/Verilog/Mutate.hs b/src/Verismith/Verilog/Mutate.hs index 586e085..a4a188b 100644 --- a/src/Verismith/Verilog/Mutate.hs +++ b/src/Verismith/Verilog/Mutate.hs @@ -244,7 +244,7 @@ instantiateMod m main = main & modItems %~ ((out ++ regIn ++ [inst]) ++) ^.. modItems . traverse . modInstId - conns = ModConn . Id <$> allVars m + conns = uncurry ModConnNamed . fmap Id <$> zip (allVars m) (allVars m) -- | Instantiate without adding wire declarations. It also does not count the -- current instantiations of the same module. |