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| author | Yann Herklotz <git@ymhg.org> | 2019-04-15 19:50:49 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-15 19:50:49 +0100 |
| commit | 705bdb142b1088676ddc3178d8677bd40ab2b1d6 (patch) | |
| tree | 74ad534cb5bb6b5156f8b468a149263ece2bdda5 | |
| parent | 398aefd8a90e8f7ade6958ccd8e006308fbf1410 (diff) | |
| download | verismith-705bdb142b1088676ddc3178d8677bd40ab2b1d6.tar.gz verismith-705bdb142b1088676ddc3178d8677bd40ab2b1d6.zip | |
Format with brittany and add right modules
| -rw-r--r-- | src/VeriFuzz/Fuzz.hs | 3 | ||||
| -rw-r--r-- | src/VeriFuzz/Sim.hs | 2 | ||||
| -rw-r--r-- | src/VeriFuzz/Verilog/BitVec.hs | 10 | ||||
| -rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 22 | ||||
| -rw-r--r-- | verifuzz.cabal | 2 |
5 files changed, 20 insertions, 19 deletions
diff --git a/src/VeriFuzz/Fuzz.hs b/src/VeriFuzz/Fuzz.hs index 1e48616..f0628e4 100644 --- a/src/VeriFuzz/Fuzz.hs +++ b/src/VeriFuzz/Fuzz.hs @@ -103,7 +103,8 @@ instance Monoid FuzzResult where type Fuzz m = StateT FuzzResult (ReaderT FuzzEnv m) runFuzz :: (Monad m) => [SynthTool] -> [SimTool] -> Fuzz m a -> m a -runFuzz synth sim m = runReaderT (evalStateT m (FuzzResult [] [])) (FuzzEnv synth sim) +runFuzz synth sim m = + runReaderT (evalStateT m (FuzzResult [] [])) (FuzzEnv synth sim) synthesisers :: (Monad m) => Fuzz m [SynthTool] synthesisers = lift $ asks getSynthesisers diff --git a/src/VeriFuzz/Sim.hs b/src/VeriFuzz/Sim.hs index 9dc21bd..f59271a 100644 --- a/src/VeriFuzz/Sim.hs +++ b/src/VeriFuzz/Sim.hs @@ -12,7 +12,7 @@ Simulator implementations. module VeriFuzz.Sim ( -- * Environment - SourceInfo(..) + SourceInfo(..) -- * Simulators -- ** Icarus , Icarus(..) diff --git a/src/VeriFuzz/Verilog/BitVec.hs b/src/VeriFuzz/Verilog/BitVec.hs index 436af7b..cdae0f7 100644 --- a/src/VeriFuzz/Verilog/BitVec.hs +++ b/src/VeriFuzz/Verilog/BitVec.hs @@ -104,12 +104,12 @@ rotateBitVec b@(BitVec s _) n | n >= 0 = iterate rotateL1 b !! n testBits a b' n' = if testBit n' a then bit b' else zeroBits width' :: Integer -> Int -width' a | a == 0 = 1 +width' a | a == 0 = 1 | otherwise = width'' a - where - width'' a' | a' == 0 = 0 - | a' == -1 = 1 - | otherwise = 1 + width'' (shiftR a' 1) + where + width'' a' | a' == 0 = 0 + | a' == -1 = 1 + | otherwise = 1 + width'' (shiftR a' 1) both :: (a -> b) -> (a, a) -> (b, b) both f (a, b) = (f a, f b) diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index 78e278e..a6ebbd9 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -20,17 +20,17 @@ module VeriFuzz.Verilog.Gen ) where -import Control.Lens hiding (Context) -import Control.Monad (replicateM) -import Control.Monad.Trans.Class (lift) -import Control.Monad.Trans.Reader hiding (local) -import Control.Monad.Trans.State.Lazy -import Data.Foldable (fold) -import Data.List.NonEmpty (toList) -import qualified Data.Text as T -import Hedgehog (Gen) -import qualified Hedgehog.Gen as Hog -import qualified Hedgehog.Range as Hog +import Control.Lens hiding (Context) +import Control.Monad (replicateM) +import Control.Monad.Trans.Class (lift) +import Control.Monad.Trans.Reader hiding (local) +import Control.Monad.Trans.State.Strict +import Data.Foldable (fold) +import Data.List.NonEmpty (toList) +import qualified Data.Text as T +import Hedgehog (Gen) +import qualified Hedgehog.Gen as Hog +import qualified Hedgehog.Range as Hog import VeriFuzz.Config import VeriFuzz.Internal import VeriFuzz.Verilog.AST diff --git a/verifuzz.cabal b/verifuzz.cabal index 646d972..c8fe982 100644 --- a/verifuzz.cabal +++ b/verifuzz.cabal @@ -34,9 +34,9 @@ library , VeriFuzz.Circuit.Internal , VeriFuzz.Circuit.Random , VeriFuzz.Config + , VeriFuzz.Fuzz , VeriFuzz.Internal , VeriFuzz.Sim - , VeriFuzz.Sim.Env , VeriFuzz.Sim.Icarus , VeriFuzz.Sim.Internal , VeriFuzz.Sim.Quartus |