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| author | Yann Herklotz <git@yannherklotz.com> | 2019-11-13 18:55:40 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-11-13 18:55:40 +0000 |
| commit | e11977ebdf04aff4c9581b6dccec9e7e95f5b2ce (patch) | |
| tree | 2de78ac934d569f2bf313d29b1e1c4ecce7f97b5 /README.md | |
| parent | 856e4fb7ec3e7ba59c6d9fceed215dde832441f5 (diff) | |
| download | verismith-e11977ebdf04aff4c9581b6dccec9e7e95f5b2ce.tar.gz verismith-e11977ebdf04aff4c9581b6dccec9e7e95f5b2ce.zip | |
Update x
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 12 |
1 files changed, 6 insertions, 6 deletions
@@ -44,17 +44,17 @@ The fuzzer generates combinational and behavioural Verilog to test the various t | Type | Issue | Confirmed | Fixed | |---------------|-------------------------------------------------------------------------------------------------------------------------------------|-----------|-------| -| Crash | [Forum 981787](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Verilog-If-statement-nesting-crash/td-p/981787) | ✓ | 𐄂 | -| Crash | [Forum 981136](https://forums.xilinx.com/t5/Synthesis/Vivado-2018-3-synthesis-crash/td-p/981136) | ✓ | 𐄂 | -| Mis-synthesis | [Forum 981789](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Unsigned-bit-extension-in-if-statement/td-p/981789) | ✓ | 𐄂 | -| Mis-synthesis | [Forum 982518](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Signed-with-shift-in-condition-synthesis-mistmatch/td-p/982518) | ✓ | 𐄂 | -| Mis-synthesis | [Forum 982419](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Bit-selection-synthesis-mismatch/td-p/982419) | ✓ | 𐄂 | +| Crash | [Forum 981787](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Verilog-If-statement-nesting-crash/td-p/981787) | ✓ | ✗ | +| Crash | [Forum 981136](https://forums.xilinx.com/t5/Synthesis/Vivado-2018-3-synthesis-crash/td-p/981136) | ✓ | ✗ | +| Mis-synthesis | [Forum 981789](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Unsigned-bit-extension-in-if-statement/td-p/981789) | ✓ | ✗ | +| Mis-synthesis | [Forum 982518](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Signed-with-shift-in-condition-synthesis-mistmatch/td-p/982518) | ✓ | ✗ | +| Mis-synthesis | [Forum 982419](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Bit-selection-synthesis-mismatch/td-p/982419) | ✓ | ✗ | ### Icarus Verilog | Type | Issue | Confirmed | Fixed | |----------------|-----------------------------------------------------------------|-----------|-------| -| Mis-simulation | [Issue 283](https://github.com/steveicarus/iverilog/issues/283) | ✓ | 𐄂 | +| Mis-simulation | [Issue 283](https://github.com/steveicarus/iverilog/issues/283) | ✓ | ✗ | ## Install the Fuzzer |