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| author | Yann Herklotz <git@yannherklotz.com> | 2019-11-14 16:49:42 +0000 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2019-11-14 16:49:42 +0000 |
| commit | e827635e34079c8ee9c9e7273a59c905274e553d (patch) | |
| tree | 5ea082d8120a740af3aeea13eb4565f2ade55c7c /bugs/yosys_9.md | |
| parent | 798f54c05376ec3b4ebbe8326d0a91eec807df3d (diff) | |
| download | verismith-e827635e34079c8ee9c9e7273a59c905274e553d.tar.gz verismith-e827635e34079c8ee9c9e7273a59c905274e553d.zip | |
Update bug reports
Diffstat (limited to 'bugs/yosys_9.md')
| -rw-r--r-- | bugs/yosys_9.md | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/bugs/yosys_9.md b/bugs/yosys_9.md index cafdf86..4e92ce7 100644 --- a/bugs/yosys_9.md +++ b/bugs/yosys_9.md @@ -1,8 +1,14 @@ # Unexpected behaviour of for loop and if statement -[ [Issue 1243](https://github.com/YosysHQ/yosys/issues/1243) ] +[ Fixed in [`39f4c10`](https://github.com/YosysHQ/yosys/commit/39f4c1096ac3b5964bfa087c2b7f2e8d5a9c1ef3) | [Issue 1243](https://github.com/YosysHQ/yosys/issues/1243) ] -## Steps to reproduce the issue +## Affected versions + +- Yosys 0.8+618 + +## Description + +### Steps to reproduce the issue Consider the following piece of code: @@ -41,7 +47,7 @@ yosys -p "read_verilog rtl.v; synth; write_verilog -noattr synth.v" I have also attached a folder containing a test bench and SymbiYosys script to compare the design to the synthesised net list. -## Expected behaviour +### Expected behaviour I would expect this to be implemented by assigning `sel` to `y`. This is actually also the output of a previous version of Yosys (`Yosys 0.8+508 (git sha1 c2ea3746, clang 8.0.0 -fPIC -Os)`) @@ -58,7 +64,7 @@ module top(y, clk, sel); endmodule ``` -## Actual behaviour +### Actual behaviour However, with Yosys, `y` is set to a constant 0. |