Add yosys 0.9 bug

1 files changed, 60 insertions, 0 deletions

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+# Constant 1 when indexing for loop variable
+
+[ Fixed by [`4b18a45`](https://github.com/YosysHQ/yosys/commit/4b18a4528ba7597bd7437837ab6d34cd8de2e110) | Not reported ]
+
+## Affected versions
+
+- Yosys 0.9
+
+## Description
+
+In the following Verilog code, the third bit in `reg1` should never be 1, because it will always be less than 2.
+
+```verilog
+module top(y, clk);
+  output y;
+  input clk;
+  reg [5:0] reg1 = 0;
+  reg signed [8:0] reg2 = 0;
+  assign y = reg2;
+  always @(posedge clk)
+    for (reg1 = 0; reg1 < 2; reg1 = reg1 + 1)
+      reg2 <= reg1[2:2];
+endmodule
+```
+
+However, in Yosys 0.9 it is compiled to:
+
+```verilog
+/* Generated by Yosys 0.9 (git sha1 1979e0b1, clang 7.0.1-8 -fPIC -Os) */
+
+module top(y, clk);
+  input clk;
+  wire [5:0] reg1;
+  wire [8:0] reg2;
+  output y;
+  reg \reg2_reg[0]  = 1'h0;
+  always @(posedge clk)
+      \reg2_reg[0]  <= 1'h1;
+  assign reg2[0] = \reg2_reg[0] ;
+  assign reg1 = 6'h00;
+  assign reg2[8:1] = 8'h00;
+  assign y = reg2[0];
+endmodule
+```
+
+The expected output is generated by the current master version of Yosys:
+
+```verilog
+/* Generated by Yosys 0.9+932 (git sha1 4b18a452, clang 7.0.1-8 -fPIC -Os) */
+
+module top(y, clk);
+  input clk;
+  wire [5:0] reg1;
+  wire [8:0] reg2;
+  output y;
+  assign reg1 = 6'h00;
+  assign reg2 = 9'h000;
+  assign y = 1'h0;
+endmodule
+```