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| author | Yann Herklotz <git@yannherklotz.com> | 2019-11-14 17:21:22 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-11-14 17:21:22 +0000 |
| commit | e4b2455be384c95a9ab87881db01841a13bfec88 (patch) | |
| tree | 457b443cd3503c1dc65511fc87569cad22974526 /bugs | |
| parent | 5150a6053de55c9564e728b1b7013f7d6074c38b (diff) | |
| download | verismith-e4b2455be384c95a9ab87881db01841a13bfec88.tar.gz verismith-e4b2455be384c95a9ab87881db01841a13bfec88.zip | |
Update description
Diffstat (limited to 'bugs')
| -rw-r--r-- | bugs/yosys_11.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bugs/yosys_11.md b/bugs/yosys_11.md index 3247135..341155c 100644 --- a/bugs/yosys_11.md +++ b/bugs/yosys_11.md @@ -23,7 +23,7 @@ module top(y, clk); endmodule ``` -However, in Yosys 0.9 it is compiled to: +However, in Yosys 0.9 it is compiled to the following, which outputs a constant one after the first clock cycle: ```verilog /* Generated by Yosys 0.9 (git sha1 1979e0b1, clang 7.0.1-8 -fPIC -Os) */ |