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| author | Yann Herklotz <git@yannherklotz.com> | 2019-06-25 22:32:21 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-06-29 16:12:46 +0100 |
| commit | 24cf9ce5bf673615ebe36f5ab5d0ff7685dfada6 (patch) | |
| tree | 87e1bde306620e6a87b6d2589618a9432c3d0a75 /data | |
| parent | a3cf56b7e2edef87181c534dea099a884ac99306 (diff) | |
| download | verismith-24cf9ce5bf673615ebe36f5ab5d0ff7685dfada6.tar.gz verismith-24cf9ce5bf673615ebe36f5ab5d0ff7685dfada6.zip | |
Add back the simulation
Diffstat (limited to 'data')
| -rw-r--r-- | data/cells_xilinx_7.v | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/data/cells_xilinx_7.v b/data/cells_xilinx_7.v index c757c2f..cc72893 100644 --- a/data/cells_xilinx_7.v +++ b/data/cells_xilinx_7.v @@ -971,19 +971,6 @@ module BUFGCTRL (O, CE0, CE1, I0, I1, IGNORE0, IGNORE1, S0, S1); end endmodule // BUFGCTRL -module BUFGDLL (O, I); - output O; - input I; - parameter DUTY_CYCLE_CORRECTION = "TRUE"; - wire clkin_int; - wire clk0_out, clk180_out, clk270_out, clk2x_out; - wire clk90_out, clkdv_out, locked_out; - CLKDLL clkdll_inst (.CLK0(clk0_out), .CLK180(clk180_out), .CLK270(clk270_out), .CLK2X(clk2x_out), .CLK90(clk90_out), .CLKDV(clkdv_out), .LOCKED(locked_out), .CLKFB(O), .CLKIN(clkin_int), .RST(1'b0)); - defparam clkdll_inst.DUTY_CYCLE_CORRECTION = DUTY_CYCLE_CORRECTION; - IBUFG ibufg_inst (.O(clkin_int), .I(I)); - BUFG bufg_inst (.O(O), .I(clk0_out)); -endmodule // BUFGDLL - module BUFG_LB ( CLKOUT, CLKIN |