| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add Cyclone 10 LP and GX | Yann Herklotz | 2019-11-14 | 1 | -33/+473 |
| * | Add enable to dffeas | Yann Herklotz | 2019-11-12 | 1 | -8/+10 |
| * | Remove second trigger for always block | Yann Herklotz | 2019-11-12 | 1 | -1/+1 |
| * | Add asynchronous load | Yann Herklotz | 2019-11-05 | 1 | -2/+6 |
| * | Fix dffeas specification | Yann Herklotz | 2019-10-31 | 1 | -4/+2 |
| * | Add description to data | Yann Herklotz | 2019-06-29 | 1 | -0/+5 |
| * | Add back the simulation | Yann Herklotz | 2019-06-29 | 1 | -13/+0 |
| * | Fix cyclone_v cell declaration | Yann Herklotz | 2019-06-02 | 1 | -46/+12 |
| * | Fix initialisation of flip flops in xilinx_7 | Yann Herklotz | 2019-05-14 | 1 | -1209/+916 |
| * | Remove modules that required $time | Yann Herklotz | 2019-05-12 | 1 | -310/+0 |
| * | Remove double inv | Yann Herklotz | 2019-05-12 | 1 | -10/+0 |
| * | Add BUF* to xilinx modules | Yann Herklotz | 2019-05-12 | 1 | -0/+963 |
| * | Add all the flip flops and latches | Yann Herklotz | 2019-05-12 | 1 | -114/+728 |
| * | Add FDE cell to xilinx | Yann Herklotz | 2019-05-12 | 1 | -0/+11 |
| * | Fix a warning in cells_cyclone_v.v | Yann Herklotz | 2019-05-06 | 1 | -241/+241 |
| * | Replace by the unisims model | Yann Herklotz | 2019-05-06 | 1 | -13/+7 |
| * | [Fix #49] Add LDPE cell to xilinx | Yann Herklotz | 2019-05-06 | 1 | -24/+39 |
| * | Fix cells_xilinx_7.v LD and FD modules | Yann Herklotz | 2019-04-23 | 1 | -17/+0 |
| * | Fix some errors in the templates | Yann Herklotz | 2019-04-23 | 1 | -0/+52 |
| * | Add new modules to fix Quartus equivalence check | Yann Herklotz | 2019-04-21 | 1 | -1/+54 |
| * | Add more primitives to data/ | Yann Herklotz | 2019-04-06 | 2 | -7/+77 |
| * | Add missing modules when using always blocks | Yann Herklotz | 2019-04-03 | 2 | -75/+108 |
| * | Add data folder with extra modules | Yann Herklotz | 2019-01-19 | 4 | -0/+418 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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