verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add Cyclone 10 LP and GX	Yann Herklotz	2019-11-14	1	-33/+473
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*	Add enable to dffeas	Yann Herklotz	2019-11-12	1	-8/+10
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*	Remove second trigger for always block	Yann Herklotz	2019-11-12	1	-1/+1
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*	Add asynchronous load	Yann Herklotz	2019-11-05	1	-2/+6
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*	Fix dffeas specification	Yann Herklotz	2019-10-31	1	-4/+2
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*	Add description to data	Yann Herklotz	2019-06-29	1	-0/+5
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*	Add back the simulation	Yann Herklotz	2019-06-29	1	-13/+0
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*	Fix cyclone_v cell declaration	Yann Herklotz	2019-06-02	1	-46/+12
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*	Fix initialisation of flip flops in xilinx_7	Yann Herklotz	2019-05-14	1	-1209/+916
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*	Remove modules that required $time	Yann Herklotz	2019-05-12	1	-310/+0
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*	Remove double inv	Yann Herklotz	2019-05-12	1	-10/+0
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*	Add BUF* to xilinx modules	Yann Herklotz	2019-05-12	1	-0/+963
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*	Add all the flip flops and latches	Yann Herklotz	2019-05-12	1	-114/+728
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*	Add FDE cell to xilinx	Yann Herklotz	2019-05-12	1	-0/+11
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*	Fix a warning in cells_cyclone_v.v	Yann Herklotz	2019-05-06	1	-241/+241
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*	Replace by the unisims model	Yann Herklotz	2019-05-06	1	-13/+7
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*	[Fix #49] Add LDPE cell to xilinx	Yann Herklotz	2019-05-06	1	-24/+39
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*	Fix cells_xilinx_7.v LD and FD modules	Yann Herklotz	2019-04-23	1	-17/+0
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*	Fix some errors in the templates	Yann Herklotz	2019-04-23	1	-0/+52
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*	Add new modules to fix Quartus equivalence check	Yann Herklotz	2019-04-21	1	-1/+54
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*	Add more primitives to data/	Yann Herklotz	2019-04-06	2	-7/+77
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*	Add missing modules when using always blocks	Yann Herklotz	2019-04-03	2	-75/+108
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*	Add data folder with extra modules	Yann Herklotz	2019-01-19	4	-0/+418
	These modules are required for comparing modules that are generated by synthesising in different simulators, as they will each synthesise to specific hardware with assumptions on what is available