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| author | Yann Herklotz <git@ymhg.org> | 2019-05-12 19:54:29 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-05-12 19:54:29 +0100 |
| commit | 8769b3dd59e59d7dd27d726cc125d5bdbd9f096a (patch) | |
| tree | 32a682eed0b648532bbbf0d5c2099a9e319ce732 /data | |
| parent | 1b35ee6626faeef57a049177ace3bdc7f2111ca7 (diff) | |
| download | verismith-8769b3dd59e59d7dd27d726cc125d5bdbd9f096a.tar.gz verismith-8769b3dd59e59d7dd27d726cc125d5bdbd9f096a.zip | |
Add FDE cell to xilinx
Diffstat (limited to 'data')
| -rw-r--r-- | data/cells_xilinx_7.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/data/cells_xilinx_7.v b/data/cells_xilinx_7.v index d7e9f67..b4b5467 100644 --- a/data/cells_xilinx_7.v +++ b/data/cells_xilinx_7.v @@ -254,3 +254,14 @@ module LDPE (Q, D, G, GE, PRE); else if (G && GE) Q <= D; endmodule + +module FDE (Q, C, CE, D); + parameter INIT = 1'b0; + output Q; + reg Q; + input C, CE, D; + + always @(posedge C) + if (CE) + Q <= D; +endmodule |