1 files changed, 11 insertions, 0 deletions
diff --git a/data/cells_xilinx_7.v b/data/cells_xilinx_7.v
index d7e9f67..b4b5467 100644
--- a/data/cells_xilinx_7.v
+++ b/data/cells_xilinx_7.v
@@ -254,3 +254,14 @@ module LDPE (Q, D, G, GE, PRE);
 	 else if (G && GE)
 	   Q <= D;
 endmodule
+
+module FDE (Q, C, CE, D);
+   parameter INIT = 1'b0;
+   output Q;
+   reg    Q;
+   input  C, CE, D;
+
+   always @(posedge C)
+	 if (CE)
+	   Q <= D;
+endmodule