| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add back the simulation | Yann Herklotz | 2019-06-29 | 1 | -13/+0 |
| * | Fix initialisation of flip flops in xilinx_7 | Yann Herklotz | 2019-05-14 | 1 | -1209/+916 |
| * | Remove modules that required $time | Yann Herklotz | 2019-05-12 | 1 | -310/+0 |
| * | Remove double inv | Yann Herklotz | 2019-05-12 | 1 | -10/+0 |
| * | Add BUF* to xilinx modules | Yann Herklotz | 2019-05-12 | 1 | -0/+963 |
| * | Add all the flip flops and latches | Yann Herklotz | 2019-05-12 | 1 | -114/+728 |
| * | Add FDE cell to xilinx | Yann Herklotz | 2019-05-12 | 1 | -0/+11 |
| * | Replace by the unisims model | Yann Herklotz | 2019-05-06 | 1 | -13/+7 |
| * | [Fix #49] Add LDPE cell to xilinx | Yann Herklotz | 2019-05-06 | 1 | -24/+39 |
| * | Fix cells_xilinx_7.v LD and FD modules | Yann Herklotz | 2019-04-23 | 1 | -17/+0 |
| * | Fix some errors in the templates | Yann Herklotz | 2019-04-23 | 1 | -0/+52 |
| * | Add more primitives to data/ | Yann Herklotz | 2019-04-06 | 1 | -0/+64 |
| * | Add missing modules when using always blocks | Yann Herklotz | 2019-04-03 | 1 | -75/+95 |
| * | Add data folder with extra modules | Yann Herklotz | 2019-01-19 | 1 | -0/+128 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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