Add missing modules when using always blocks

2 files changed, 108 insertions, 75 deletions

diff --git a/data/cells_xilinx_7.v b/data/cells_xilinx_7.v
index 01522a1..d729549 100644
--- a/data/cells_xilinx_7.v
+++ b/data/cells_xilinx_7.v
@@ -2,127 +2,147 @@
 // Based on the simulation models from /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/
 
 module IBUF(O, I);
-output O;
-input  I;
-assign O = I;
+   output O;
+   input  I;
+   assign O = I;
 endmodule
 
 module OBUF(O, I);
-output O;
-input  I;
-assign O = I;
+   output O;
+   input  I;
+   assign O = I;
 endmodule
 
 module OBUFT(O, I, T);
-output O;
-input  I, T;
-assign O = T ? 1'bz : I;
+   output O;
+   input  I, T;
+   assign O = T ? 1'bz : I;
 endmodule
 
 module GND(G);
-output G;
-assign G = 0;
+   output G;
+   assign G = 0;
 endmodule
 
 module INV(O, I);
-input I;
-output O;
-assign O = !I;
+   input I;
+   output O;
+   assign O = !I;
 endmodule
 
 module LUT1(O, I0);
-parameter INIT = 0;
-input I0;
-wire [1:0] lutdata = INIT;
-wire [0:0] idx = { I0 };
-output O;
-assign O = lutdata[idx];
+   parameter INIT = 0;
+   input I0;
+   wire [1:0] lutdata = INIT;
+   wire [0:0] idx = { I0 };
+   output     O;
+   assign O = lutdata[idx];
 endmodule
 
 module LUT2(O, I0, I1);
-parameter INIT = 0;
-input I0, I1;
-wire [3:0] lutdata = INIT;
-wire [1:0] idx = { I1, I0 };
-output O;
-assign O = lutdata[idx];
+   parameter INIT = 0;
+   input I0, I1;
+   wire [3:0] lutdata = INIT;
+   wire [1:0] idx = { I1, I0 };
+   output     O;
+   assign O = lutdata[idx];
 endmodule
 
 module LUT3(O, I0, I1, I2);
-parameter INIT = 0;
-input I0, I1, I2;
-wire [7:0] lutdata = INIT;
-wire [2:0] idx = { I2, I1, I0 };
-output O;
-assign O = lutdata[idx];
+   parameter INIT = 0;
+   input I0, I1, I2;
+   wire [7:0] lutdata = INIT;
+   wire [2:0] idx = { I2, I1, I0 };
+   output     O;
+   assign O = lutdata[idx];
 endmodule
 
 module LUT4(O, I0, I1, I2, I3);
-parameter INIT = 0;
-input I0, I1, I2, I3;
-wire [15:0] lutdata = INIT;
-wire [3:0] idx = { I3, I2, I1, I0 };
-output O;
-assign O = lutdata[idx];
+   parameter INIT = 0;
+   input I0, I1, I2, I3;
+   wire [15:0] lutdata = INIT;
+   wire [3:0]  idx = { I3, I2, I1, I0 };
+   output      O;
+   assign O = lutdata[idx];
 endmodule
 
 module LUT5(O, I0, I1, I2, I3, I4);
-parameter INIT = 0;
-input I0, I1, I2, I3, I4;
-wire [31:0] lutdata = INIT;
-wire [4:0] idx = { I4, I3, I2, I1, I0 };
-output O;
-assign O = lutdata[idx];
+   parameter INIT = 0;
+   input I0, I1, I2, I3, I4;
+   wire [31:0] lutdata = INIT;
+   wire [4:0]  idx = { I4, I3, I2, I1, I0 };
+   output      O;
+   assign O = lutdata[idx];
 endmodule
 
 module LUT6(O, I0, I1, I2, I3, I4, I5);
-parameter INIT = 0;
-input I0, I1, I2, I3, I4, I5;
-wire [63:0] lutdata = INIT;
-wire [5:0] idx = { I5, I4, I3, I2, I1, I0 };
-output O;
-assign O = lutdata[idx];
+   parameter INIT = 0;
+   input I0, I1, I2, I3, I4, I5;
+   wire [63:0] lutdata = INIT;
+   wire [5:0]  idx = { I5, I4, I3, I2, I1, I0 };
+   output      O;
+   assign O = lutdata[idx];
 endmodule
 
 module MUXCY(O, CI, DI, S);
-input CI, DI, S;
-output O;
-assign O = S ? CI : DI;
+   input CI, DI, S;
+   output O;
+   assign O = S ? CI : DI;
 endmodule
 
 module MUXF7(O, I0, I1, S);
-input I0, I1, S;
-output O;
-assign O = S ? I1 : I0;
+   input I0, I1, S;
+   output O;
+   assign O = S ? I1 : I0;
 endmodule
 
 module MUXF8(O, I0, I1, S);
-input I0, I1, S;
-output O;
-assign O = S ? I1 : I0;
+   input I0, I1, S;
+   output O;
+   assign O = S ? I1 : I0;
 endmodule
 
 module VCC(P);
-output P;
-assign P = 1;
+   output P;
+   assign P = 1;
 endmodule
 
 module XORCY(O, CI, LI);
-input CI, LI;
-output O;
-assign O = CI ^ LI;
+   input CI, LI;
+   output O;
+   assign O = CI ^ LI;
 endmodule
 
 module CARRY4(CO, O, CI, CYINIT, DI, S);
-output [3:0] CO, O;
-input  CI, CYINIT;
-input  [3:0] DI, S;
-wire ci_or_cyinit;
-assign O = S ^ {CO[2:0], ci_or_cyinit};
-assign CO[0] = S[0] ? ci_or_cyinit : DI[0];
-assign CO[1] = S[1] ? CO[0] : DI[1];
-assign CO[2] = S[2] ? CO[1] : DI[2];
-assign CO[3] = S[3] ? CO[2] : DI[3];
-assign ci_or_cyinit = CI | CYINIT;
+   output [3:0] CO, O;
+   input        CI, CYINIT;
+   input [3:0]  DI, S;
+   wire         ci_or_cyinit;
+   assign O = S ^ {CO[2:0], ci_or_cyinit};
+   assign CO[0] = S[0] ? ci_or_cyinit : DI[0];
+   assign CO[1] = S[1] ? CO[0] : DI[1];
+   assign CO[2] = S[2] ? CO[1] : DI[2];
+   assign CO[3] = S[3] ? CO[2] : DI[3];
+   assign ci_or_cyinit = CI | CYINIT;
+endmodule
+
+module LDCE (Q, CLR, D, G, GE);
+   parameter [0:0] INIT = 1'b0;
+   parameter [0:0] IS_CLR_INVERTED = 1'b0;
+   parameter [0:0] IS_G_INVERTED = 1'b0;
+
+   output Q;
+   reg    Q = INIT;
+
+   input  CLR, D, G, GE;
+   wire   CLR_in, G_in;
+
+   assign CLR_in = IS_CLR_INVERTED ^ CLR;
+   assign G_in = IS_G_INVERTED ^ G;
+
+   always @( CLR_in or D or G_in or GE)
+     if (CLR_in)
+       Q <= 0;
+     else if (G_in && GE)
+       Q <= D;
 endmodule
-
diff --git a/data/cells_yosys.v b/data/cells_yosys.v
new file mode 100644
index 0000000..48f9c66
--- /dev/null
+++ b/data/cells_yosys.v
@@ -0,0 +1,13 @@
+// Taken from yosys verilog files.
+
+module \$_DLATCH_N_ (E, D, Q);
+   wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+   input         E, D;
+   output        Q = !E ? D : Q;
+endmodule
+
+module \$_DLATCH_P_ (E, D, Q);
+   wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+   input         E, D;
+   output        Q = E ? D : Q;
+endmodule