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| author | Yann Herklotz <git@yannherklotz.com> | 2019-11-12 21:53:58 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-11-12 21:53:58 +0000 |
| commit | 25f2c7c948cfb5053747e9450ceb30692d5024f2 (patch) | |
| tree | fab1c411b5105fb850f85ec1d25ff6a0173bc36a /data | |
| parent | 02849780204c36fd9c130a398c0a6901b461f8f5 (diff) | |
| download | verismith-25f2c7c948cfb5053747e9450ceb30692d5024f2.tar.gz verismith-25f2c7c948cfb5053747e9450ceb30692d5024f2.zip | |
Add enable to dffeas
Diffstat (limited to 'data')
| -rw-r--r-- | data/cells_cyclone_v.v | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/data/cells_cyclone_v.v b/data/cells_cyclone_v.v index ad8b977..246283f 100644 --- a/data/cells_cyclone_v.v +++ b/data/cells_cyclone_v.v @@ -221,14 +221,16 @@ module dffeas (d, clk, ena, clrn, prn, aload, asdata, sclr, sload, devclrn, devp output reg q = 0; always @(posedge clk) begin - if (sclr == 1'b1) - q <= 0; - else if (aload == 1'b1) - q <= asdata; - else if (sload == 1'b1) - q <= asdata; - else - q <= d; + if (ena == 1'b1) begin + if (sclr == 1'b1) + q <= 0; + else if (aload == 1'b1) + q <= asdata; + else if (sload == 1'b1) + q <= asdata; + else + q <= d; + end end endmodule |